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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3864 extern const TargetRegisterClass GPRCRegClass;
References
gen/lib/Target/PowerPC/PPCGenFastISel.inc 68 return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
122 return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
184 return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
247 return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
315 return fastEmitInst_r(PPC::EFSABS, &PPC::GPRCRegClass, Op0, Op0IsKill);
570 return fastEmitInst_r(PPC::EFSNEG, &PPC::GPRCRegClass, Op0, Op0IsKill);
678 return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0, Op0IsKill);
709 return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
718 return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
760 return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
769 return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
1047 return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0, Op0IsKill);
1123 return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0, Op0IsKill);
1504 return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
1536 return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
1747 return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1820 return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1842 return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1870 return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1928 return fastEmitInst_rr(PPC::EFSADD, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2014 return fastEmitInst_rr(PPC::EFSDIV, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2176 return fastEmitInst_rr(PPC::EFSMUL, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2259 return fastEmitInst_rr(PPC::EFSSUB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2347 return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2380 return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2402 return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2430 return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2466 return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2488 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2619 return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2675 return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2702 return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2822 return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2921 return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2954 return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2990 return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3030 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3085 return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3140 return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3276 return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3396 return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3411 return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3426 return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 4146 &PPC::GPRCRegClass,
4782 &PPC::GPRCRegClass,
lib/Target/PowerPC/PPCFastISel.cpp 472 (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
630 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
934 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
940 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
992 DestReg = createResultReg(&PPC::GPRCRegClass);
1230 DestReg = createResultReg(&PPC::GPRCRegClass);
1232 Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1234 Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1284 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1444 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1456 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1537 ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1766 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1775 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1890 SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
2005 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2117 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2215 ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2397 &PPC::GPRCRegClass);
2425 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2439 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2453 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
lib/Target/PowerPC/PPCFrameLowering.cpp 664 &PPC::GPRCRegClass);
1889 if (PPC::GPRCRegClass.contains(Reg)) {
1987 } else if (PPC::GPRCRegClass.contains(BP)) {
2107 const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
2167 if (!PPC::G8RCRegClass.contains(Reg) && !PPC::GPRCRegClass.contains(Reg)) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 394 Register InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
395 Register UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
450 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
lib/Target/PowerPC/PPCISelLowering.cpp 145 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
148 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
3490 RC = &PPC::GPRCRegClass;
3496 RC = &PPC::GPRCRegClass;
3505 RC = &PPC::GPRCRegClass;
3636 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
4253 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4276 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4299 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4444 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
10356 : &PPC::GPRCRegClass);
10388 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
10459 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
10460 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
10765 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11024 Register ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11274 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11275 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
11467 Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
14319 return std::make_pair(0U, &PPC::GPRCRegClass);
14327 return std::make_pair(0U, &PPC::GPRCRegClass);
14376 PPC::GPRCRegClass.contains(R.first))
lib/Target/PowerPC/PPCInstrInfo.cpp 775 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
809 PPC::GPRCRegClass.hasSubClassEq(RC) ||
933 PPC::GPRCRegClass.contains(DestReg)) {
951 PPC::GPRCRegClass.contains(DestReg)) {
971 PPC::GPRCRegClass.contains(DestReg)) {
975 } else if (PPC::GPRCRegClass.contains(SrcReg) &&
983 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
1034 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1072 if (PPC::GPRCRegClass.contains(Reg) ||
1120 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1158 if (PPC::GPRCRegClass.contains(Reg) ||
3839 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
lib/Target/PowerPC/PPCRegisterInfo.cpp 138 return &PPC::GPRCRegClass;
468 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
528 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
700 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
744 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
823 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
871 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
897 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1094 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
lib/Target/PowerPC/PPCSubtarget.cpp 208 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
tools/llvm-exegesis/lib/PowerPC/Target.cpp 56 if (PPC::GPRCRegClass.contains(Reg))