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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3875 extern const TargetRegisterClass G8RCRegClass;
References
gen/lib/Target/PowerPC/PPCGenFastISel.inc 35 return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
104 return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
128 return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
190 return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
256 return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
1033 return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
1511 return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
1542 return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
1753 return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1826 return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1848 return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1876 return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2353 return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2386 return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2408 return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2436 return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2472 return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2684 return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2828 return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2930 return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2960 return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2996 return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3282 return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3299 return fastEmitInst_ri(PPC::EXTSWSLI_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3471 return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3486 return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3501 return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 4175 &PPC::G8RCRegClass,
4793 &PPC::G8RCRegClass,
lib/Target/PowerPC/PPCFastISel.cpp 496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
1024 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1119 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1300 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1444 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1456 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1766 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1775 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
2215 ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2396 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2426 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2440 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2454 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
lib/Target/PowerPC/PPCFrameLowering.cpp 663 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
1897 } else if (PPC::G8RCRegClass.contains(Reg)) {
1984 if (PPC::G8RCRegClass.contains(BP)) {
2108 const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
2167 if (!PPC::G8RCRegClass.contains(Reg) && !PPC::GPRCRegClass.contains(Reg)) {
lib/Target/PowerPC/PPCISelLowering.cpp 537 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
3840 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3875 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3899 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3958 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4085 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4251 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4274 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4317 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4442 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
6948 if (PPC::G8RCRegClass.contains(*I))
10355 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
10459 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
10765 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11274 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11467 Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
11532 assert((RegInfo.getRegClass(DestReg) == &PPC::G8RCRegClass) &&
11539 assert((RegInfo.getRegClass(SrcReg) == &PPC::G8RCRegClass) &&
11589 Register OldFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11593 Register ImDefReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11594 Register ExtSrcReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11605 Register NewFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
14318 return std::make_pair(0U, &PPC::G8RCRegClass);
14378 PPC::sub_32, &PPC::G8RCRegClass),
14379 &PPC::G8RCRegClass);
15036 if (PPC::G8RCRegClass.contains(*I))
15037 RC = &PPC::G8RCRegClass;
lib/Target/PowerPC/PPCInstrInfo.cpp 777 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
806 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
946 PPC::G8RCRegClass.contains(DestReg)) {
955 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
964 PPC::G8RCRegClass.contains(DestReg)) {
985 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
1037 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1075 } else if (PPC::G8RCRegClass.contains(Reg) ||
1123 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1161 } else if (PPC::G8RCRegClass.contains(Reg) ||
lib/Target/PowerPC/PPCMIPeephole.cpp 655 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
lib/Target/PowerPC/PPCRegisterInfo.cpp 137 return &PPC::G8RCRegClass;
464 RC == &PPC::G8RCRegClass) {
527 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
654 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
699 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
743 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
822 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1093 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
lib/Target/PowerPC/PPCSubtarget.cpp 208 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
tools/llvm-exegesis/lib/PowerPC/Target.cpp 58 if (PPC::G8RCRegClass.contains(Reg))