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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 6257 { 9233 /* slw */, PPC::SLW, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, AMFBS_None, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
gen/lib/Target/PowerPC/PPCGenDAGISel.inc27490 /* 66599*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::SLW), 0,
28107 /* 67755*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::SLW), 0,
gen/lib/Target/PowerPC/PPCGenFastISel.inc 2488 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3030 return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc12330 { PPC::SLWo, PPC::SLW },
12494 { PPC::SLW, PPC::SLWo },
gen/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc 2583 case PPC::SLW:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 6080 if (Op32.getMachineOpcode() == PPC::SLW ||
6293 case PPC::SLW: NewOpcode = PPC::SLW8; break;
lib/Target/PowerPC/PPCISelLowering.cpp10532 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
10541 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
11357 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
11360 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
11371 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
lib/Target/PowerPC/PPCInstrInfo.cpp 3097 case PPC::SLW:
3127 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
3761 Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3947 Opcode == PPC::SLW || Opcode == PPC::SLWo ||