|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 3299 { 391, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #391 = BCDCPSGNo
3307 { 399, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #399 = BCDUSo
3308 { 400, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #400 = BCDUTRUNCo
4568 { 1660, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1660 = VABSDUB
4569 { 1661, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1661 = VABSDUH
4570 { 1662, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1662 = VABSDUW
4571 { 1663, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1663 = VADDCUQ
4572 { 1664, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1664 = VADDCUW
4575 { 1667, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1667 = VADDFP
4576 { 1668, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1668 = VADDSBS
4577 { 1669, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1669 = VADDSHS
4578 { 1670, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1670 = VADDSWS
4579 { 1671, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1671 = VADDUBM
4580 { 1672, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1672 = VADDUBS
4581 { 1673, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1673 = VADDUDM
4582 { 1674, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1674 = VADDUHM
4583 { 1675, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1675 = VADDUHS
4584 { 1676, 3, 1, 4, 163, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1676 = VADDUQM
4585 { 1677, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1677 = VADDUWM
4586 { 1678, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1678 = VADDUWS
4587 { 1679, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1679 = VAND
4588 { 1680, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1680 = VANDC
4589 { 1681, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1681 = VAVGSB
4590 { 1682, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1682 = VAVGSH
4591 { 1683, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1683 = VAVGSW
4592 { 1684, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1684 = VAVGUB
4593 { 1685, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1685 = VAVGUH
4594 { 1686, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1686 = VAVGUW
4595 { 1687, 3, 1, 4, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1687 = VBPERMD
4596 { 1688, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1688 = VBPERMQ
4601 { 1693, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1693 = VCIPHER
4602 { 1694, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1694 = VCIPHERLAST
4608 { 1700, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1700 = VCMPBFP
4609 { 1701, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1701 = VCMPBFPo
4610 { 1702, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1702 = VCMPEQFP
4611 { 1703, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1703 = VCMPEQFPo
4612 { 1704, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1704 = VCMPEQUB
4613 { 1705, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1705 = VCMPEQUBo
4614 { 1706, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1706 = VCMPEQUD
4615 { 1707, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1707 = VCMPEQUDo
4616 { 1708, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1708 = VCMPEQUH
4617 { 1709, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1709 = VCMPEQUHo
4618 { 1710, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1710 = VCMPEQUW
4619 { 1711, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1711 = VCMPEQUWo
4620 { 1712, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1712 = VCMPGEFP
4621 { 1713, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1713 = VCMPGEFPo
4622 { 1714, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1714 = VCMPGTFP
4623 { 1715, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1715 = VCMPGTFPo
4624 { 1716, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1716 = VCMPGTSB
4625 { 1717, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1717 = VCMPGTSBo
4626 { 1718, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1718 = VCMPGTSD
4627 { 1719, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1719 = VCMPGTSDo
4628 { 1720, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1720 = VCMPGTSH
4629 { 1721, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1721 = VCMPGTSHo
4630 { 1722, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1722 = VCMPGTSW
4631 { 1723, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1723 = VCMPGTSWo
4632 { 1724, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1724 = VCMPGTUB
4633 { 1725, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1725 = VCMPGTUBo
4634 { 1726, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1726 = VCMPGTUD
4635 { 1727, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1727 = VCMPGTUDo
4636 { 1728, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1728 = VCMPGTUH
4637 { 1729, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1729 = VCMPGTUHo
4638 { 1730, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1730 = VCMPGTUW
4639 { 1731, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1731 = VCMPGTUWo
4640 { 1732, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1732 = VCMPNEB
4641 { 1733, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1733 = VCMPNEBo
4642 { 1734, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1734 = VCMPNEH
4643 { 1735, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1735 = VCMPNEHo
4644 { 1736, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1736 = VCMPNEW
4645 { 1737, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1737 = VCMPNEWo
4646 { 1738, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1738 = VCMPNEZB
4647 { 1739, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1739 = VCMPNEZBo
4648 { 1740, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1740 = VCMPNEZH
4649 { 1741, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1741 = VCMPNEZHo
4650 { 1742, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1742 = VCMPNEZW
4651 { 1743, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #1743 = VCMPNEZWo
4661 { 1753, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1753 = VEQV
4690 { 1782, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1782 = VMAXFP
4691 { 1783, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1783 = VMAXSB
4692 { 1784, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1784 = VMAXSD
4693 { 1785, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1785 = VMAXSH
4694 { 1786, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1786 = VMAXSW
4695 { 1787, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1787 = VMAXUB
4696 { 1788, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1788 = VMAXUD
4697 { 1789, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1789 = VMAXUH
4698 { 1790, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1790 = VMAXUW
4701 { 1793, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1793 = VMINFP
4702 { 1794, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1794 = VMINSB
4703 { 1795, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1795 = VMINSD
4704 { 1796, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1796 = VMINSH
4705 { 1797, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1797 = VMINSW
4706 { 1798, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1798 = VMINUB
4707 { 1799, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1799 = VMINUD
4708 { 1800, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1800 = VMINUH
4709 { 1801, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1801 = VMINUW
4711 { 1803, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1803 = VMRGEW
4712 { 1804, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1804 = VMRGHB
4713 { 1805, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1805 = VMRGHH
4714 { 1806, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1806 = VMRGHW
4715 { 1807, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1807 = VMRGLB
4716 { 1808, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1808 = VMRGLH
4717 { 1809, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1809 = VMRGLW
4718 { 1810, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1810 = VMRGOW
4726 { 1818, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1818 = VMUL10ECUQ
4727 { 1819, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1819 = VMUL10EUQ
4729 { 1821, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1821 = VMULESB
4730 { 1822, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1822 = VMULESH
4731 { 1823, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1823 = VMULESW
4732 { 1824, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1824 = VMULEUB
4733 { 1825, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1825 = VMULEUH
4734 { 1826, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1826 = VMULEUW
4735 { 1827, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1827 = VMULOSB
4736 { 1828, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1828 = VMULOSH
4737 { 1829, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1829 = VMULOSW
4738 { 1830, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1830 = VMULOUB
4739 { 1831, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1831 = VMULOUH
4740 { 1832, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1832 = VMULOUW
4741 { 1833, 3, 1, 4, 143, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1833 = VMULUWM
4742 { 1834, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1834 = VNAND
4743 { 1835, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1835 = VNCIPHER
4744 { 1836, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1836 = VNCIPHERLAST
4748 { 1840, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1840 = VNOR
4749 { 1841, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1841 = VOR
4750 { 1842, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1842 = VORC
4754 { 1846, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1846 = VPKPX
4755 { 1847, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1847 = VPKSDSS
4756 { 1848, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1848 = VPKSDUS
4757 { 1849, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1849 = VPKSHSS
4758 { 1850, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1850 = VPKSHUS
4759 { 1851, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1851 = VPKSWSS
4760 { 1852, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1852 = VPKSWUS
4761 { 1853, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1853 = VPKUDUM
4762 { 1854, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1854 = VPKUDUS
4763 { 1855, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1855 = VPKUHUM
4764 { 1856, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1856 = VPKUHUS
4765 { 1857, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1857 = VPKUWUM
4766 { 1858, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1858 = VPKUWUS
4767 { 1859, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1859 = VPMSUMB
4768 { 1860, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1860 = VPMSUMD
4769 { 1861, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1861 = VPMSUMH
4770 { 1862, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1862 = VPMSUMW
4783 { 1875, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1875 = VRLB
4784 { 1876, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1876 = VRLD
4786 { 1878, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1878 = VRLDNM
4787 { 1879, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1879 = VRLH
4788 { 1880, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1880 = VRLW
4790 { 1882, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1882 = VRLWNM
4796 { 1888, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1888 = VSL
4797 { 1889, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1889 = VSLB
4798 { 1890, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1890 = VSLD
4800 { 1892, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1892 = VSLH
4801 { 1893, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1893 = VSLO
4802 { 1894, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1894 = VSLV
4803 { 1895, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1895 = VSLW
4812 { 1904, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1904 = VSR
4813 { 1905, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1905 = VSRAB
4814 { 1906, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1906 = VSRAD
4815 { 1907, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1907 = VSRAH
4816 { 1908, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1908 = VSRAW
4817 { 1909, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1909 = VSRB
4818 { 1910, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1910 = VSRD
4819 { 1911, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1911 = VSRH
4820 { 1912, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1912 = VSRO
4821 { 1913, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1913 = VSRV
4822 { 1914, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1914 = VSRW
4823 { 1915, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1915 = VSUBCUQ
4824 { 1916, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1916 = VSUBCUW
4827 { 1919, 3, 1, 4, 143, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1919 = VSUBFP
4828 { 1920, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1920 = VSUBSBS
4829 { 1921, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1921 = VSUBSHS
4830 { 1922, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1922 = VSUBSWS
4831 { 1923, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1923 = VSUBUBM
4832 { 1924, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1924 = VSUBUBS
4833 { 1925, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1925 = VSUBUDM
4834 { 1926, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1926 = VSUBUHM
4835 { 1927, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1927 = VSUBUHS
4836 { 1928, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1928 = VSUBUQM
4837 { 1929, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1929 = VSUBUWM
4838 { 1930, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1930 = VSUBUWS
4839 { 1931, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1931 = VSUM2SWS
4840 { 1932, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1932 = VSUM4SBS
4841 { 1933, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1933 = VSUM4SHS
4842 { 1934, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1934 = VSUM4UBS
4843 { 1935, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1935 = VSUMSWS
4852 { 1944, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1944 = VXOR
4873 { 1965, 3, 1, 4, 165, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1965 = XSADDQP
4874 { 1966, 3, 1, 4, 165, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1966 = XSADDQPO
4886 { 1978, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1978 = XSCPSGNQP
4915 { 2007, 3, 1, 4, 169, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2007 = XSDIVQP
4916 { 2008, 3, 1, 4, 169, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2008 = XSDIVQPO
4939 { 2031, 3, 1, 4, 167, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2031 = XSMULQP
4940 { 2032, 3, 1, 4, 167, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2032 = XSMULQPO
4976 { 2068, 3, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2068 = XSSUBQP
4977 { 2069, 3, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2069 = XSSUBQPO