reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/PowerPC/PPCGenInstrInfo.inc
 3089   { 181,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #181 = CLRRWI
 3090   { 182,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #182 = CLRRWIo
 3135   { 227,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #227 = ROTRWI
 3136   { 228,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #228 = ROTRWIo
 3139   { 231,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #231 = SLWI
 3140   { 232,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #232 = SLWIo
 3147   { 239,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #239 = SRWI
 3148   { 240,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #240 = SRWIo
 3150   { 242,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #242 = SUBI
 3151   { 243,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #243 = SUBIC
 3152   { 244,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #244 = SUBICo
 3153   { 245,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #245 = SUBIS
 3160   { 252,	3,	1,	4,	116,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #252 = ADD4TLS
 3176   { 268,	3,	1,	4,	115,	0, 0xcULL, nullptr, ImplicitList4, OperandInfo40, -1 ,nullptr },  // Inst #268 = ADDIC
 3178   { 270,	3,	1,	4,	115,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, ImplicitList5, OperandInfo40, -1 ,nullptr },  // Inst #270 = ADDICo
 3217   { 309,	3,	1,	4,	115,	0, 0x8ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr },  // Inst #309 = ANDISo
 3219   { 311,	3,	1,	4,	115,	0, 0x8ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr },  // Inst #311 = ANDIo
 3405   { 497,	3,	0,	4,	176,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #497 = CP_COPY
 3407   { 499,	3,	0,	4,	177,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #499 = CP_PASTE
 3410   { 502,	3,	0,	4,	203,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr },  // Inst #502 = CP_PASTEo
 3860   { 952,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList25, OperandInfo40, -1 ,nullptr },  // Inst #952 = GETtlsADDR32
 3862   { 954,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList25, OperandInfo40, -1 ,nullptr },  // Inst #954 = GETtlsldADDR32
 3950   { 1042,	3,	1,	4,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1042 = LSWI
 3961   { 1053,	3,	1,	4,	289,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1053 = LWAT
 4095   { 1187,	3,	1,	4,	147,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1187 = MULLI
 4125   { 1217,	3,	1,	4,	116,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1217 = ORI
 4127   { 1219,	3,	1,	4,	116,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1219 = ORIS
 4396   { 1488,	3,	1,	4,	112,	0, 0x8ULL, nullptr, ImplicitList4, OperandInfo40, -1 ,nullptr },  // Inst #1488 = SRADI_32
 4400   { 1492,	3,	1,	4,	132,	0, 0x8ULL, nullptr, ImplicitList4, OperandInfo40, -1 ,nullptr },  // Inst #1492 = SRAWI
 4401   { 1493,	3,	1,	4,	254,	0, 0x8ULL, nullptr, ImplicitList5, OperandInfo40, -1 ,nullptr },  // Inst #1493 = SRAWIo
 4460   { 1552,	3,	0,	4,	219,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1552 = STSWI
 4468   { 1560,	3,	0,	4,	290,	0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1560 = STWAT
 4510   { 1602,	3,	1,	4,	115,	0, 0x8ULL, nullptr, ImplicitList4, OperandInfo40, -1 ,nullptr },  // Inst #1602 = SUBFIC
 4865   { 1957,	3,	1,	4,	116,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1957 = XORI
 4867   { 1959,	3,	1,	4,	116,	0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1959 = XORIS