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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2908 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
2918 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
2922 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
2934 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
2995 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
2996 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
3059 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3275 { 367, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #367 = B
3276 { 368, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #368 = BA
3314 { 406, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #406 = BCLalways
3322 { 414, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #414 = BDNZ
3323 { 415, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #415 = BDNZ8
3324 { 416, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #416 = BDNZA
3325 { 417, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #417 = BDNZAm
3326 { 418, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #418 = BDNZAp
3327 { 419, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #419 = BDNZL
3328 { 420, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #420 = BDNZLA
3329 { 421, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #421 = BDNZLAm
3330 { 422, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #422 = BDNZLAp
3338 { 430, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #430 = BDNZLm
3339 { 431, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #431 = BDNZLp
3340 { 432, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #432 = BDNZm
3341 { 433, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #433 = BDNZp
3342 { 434, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #434 = BDZ
3343 { 435, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #435 = BDZ8
3344 { 436, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #436 = BDZA
3345 { 437, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #437 = BDZAm
3346 { 438, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #438 = BDZAp
3347 { 439, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #439 = BDZL
3348 { 440, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #440 = BDZLA
3349 { 441, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #441 = BDZLAm
3350 { 442, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #442 = BDZLAp
3358 { 450, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #450 = BDZLm
3359 { 451, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #451 = BDZLp
3360 { 452, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #452 = BDZm
3361 { 453, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList9, OperandInfo2, -1 ,nullptr }, // Inst #453 = BDZp
3368 { 460, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #460 = BLA
3369 { 461, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo2, -1 ,nullptr }, // Inst #461 = BLA8
3370 { 462, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo2, -1 ,nullptr }, // Inst #462 = BLA8_NOP
3456 { 548, 1, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, PPC::DeprecatedDST ,nullptr }, // Inst #548 = DSS
3526 { 618, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #618 = EH_SjLj_Setup
4005 { 1097, 1, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1097 = MBAR
4056 { 1148, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1148 = MTFSB0
4057 { 1149, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1149 = MTFSB1
4307 { 1399, 1, 0, 4, 121, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1399 = RFEBB
4529 { 1621, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = TAILBA
4530 { 1622, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1622 = TAILBA8
4533 { 1625, 1, 0, 4, 122, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1625 = TBEGIN
4545 { 1637, 1, 0, 4, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1637 = TEND
4563 { 1655, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1655 = TSR