|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 4235 { 1327, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1327 = QVLFCDUX
4236 { 1328, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1328 = QVLFCDUXA
4237 { 1329, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1329 = QVLFCDX
4238 { 1330, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1330 = QVLFCDXA
4239 { 1331, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1331 = QVLFCSUX
4240 { 1332, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1332 = QVLFCSUXA
4241 { 1333, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1333 = QVLFCSX
4242 { 1334, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1334 = QVLFCSXA
4245 { 1337, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1337 = QVLFDUXA
4246 { 1338, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1338 = QVLFDX
4247 { 1339, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1339 = QVLFDXA
4249 { 1341, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1341 = QVLFIWAX
4250 { 1342, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1342 = QVLFIWAXA
4251 { 1343, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1343 = QVLFIWZX
4252 { 1344, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1344 = QVLFIWZXA
4254 { 1346, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1346 = QVLFSUXA
4255 { 1347, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1347 = QVLFSX
4256 { 1348, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1348 = QVLFSXA
4259 { 1351, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1351 = QVLPCLDX
4260 { 1352, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1352 = QVLPCLSX
4262 { 1354, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1354 = QVLPCRDX
4263 { 1355, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1355 = QVLPCRSX
4264 { 1356, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1356 = QVSTFCDUX
4265 { 1357, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1357 = QVSTFCDUXA
4266 { 1358, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1358 = QVSTFCDUXI
4267 { 1359, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1359 = QVSTFCDUXIA
4268 { 1360, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1360 = QVSTFCDX
4269 { 1361, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1361 = QVSTFCDXA
4270 { 1362, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1362 = QVSTFCDXI
4271 { 1363, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1363 = QVSTFCDXIA
4272 { 1364, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1364 = QVSTFCSUX
4273 { 1365, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1365 = QVSTFCSUXA
4274 { 1366, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1366 = QVSTFCSUXI
4275 { 1367, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1367 = QVSTFCSUXIA
4276 { 1368, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1368 = QVSTFCSX
4277 { 1369, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1369 = QVSTFCSXA
4278 { 1370, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1370 = QVSTFCSXI
4279 { 1371, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1371 = QVSTFCSXIA
4282 { 1374, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1374 = QVSTFDUXA
4283 { 1375, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1375 = QVSTFDUXI
4284 { 1376, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1376 = QVSTFDUXIA
4285 { 1377, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1377 = QVSTFDX
4286 { 1378, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1378 = QVSTFDXA
4287 { 1379, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1379 = QVSTFDXI
4288 { 1380, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1380 = QVSTFDXIA
4290 { 1382, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1382 = QVSTFIWX
4291 { 1383, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1383 = QVSTFIWXA
4293 { 1385, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1385 = QVSTFSUXA
4294 { 1386, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1386 = QVSTFSUXI
4295 { 1387, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1387 = QVSTFSUXIA
4297 { 1389, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1389 = QVSTFSX
4298 { 1390, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1390 = QVSTFSXA
4299 { 1391, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1391 = QVSTFSXI
4300 { 1392, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1392 = QVSTFSXIA