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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 5818 { 6654 /* mfamr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_29, AMFBS_None, { MCK_RegGPRC }, },
5819 { 6660 /* mfasr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_280, AMFBS_None, { MCK_RegGPRC }, },
5829 { 6722 /* mfcfar */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_28, AMFBS_None, { MCK_RegGPRC }, },
5832 { 6740 /* mfdar */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_19, AMFBS_None, { MCK_RegGPRC }, },
5833 { 6746 /* mfdbatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_537, AMFBS_None, { MCK_RegGPRC, MCK_0 }, },
5834 { 6746 /* mfdbatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_539, AMFBS_None, { MCK_RegGPRC, MCK_1 }, },
5835 { 6746 /* mfdbatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_541, AMFBS_None, { MCK_RegGPRC, MCK_2 }, },
5836 { 6746 /* mfdbatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_543, AMFBS_None, { MCK_RegGPRC, MCK_3 }, },
5837 { 6754 /* mfdbatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_536, AMFBS_None, { MCK_RegGPRC, MCK_0 }, },
5838 { 6754 /* mfdbatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_538, AMFBS_None, { MCK_RegGPRC, MCK_1 }, },
5839 { 6754 /* mfdbatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_540, AMFBS_None, { MCK_RegGPRC, MCK_2 }, },
5840 { 6754 /* mfdbatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_542, AMFBS_None, { MCK_RegGPRC, MCK_3 }, },
5841 { 6762 /* mfdccr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_1018, AMFBS_None, { MCK_RegGPRC }, },
5843 { 6775 /* mfdear */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_981, AMFBS_None, { MCK_RegGPRC }, },
5844 { 6782 /* mfdec */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_22, AMFBS_None, { MCK_RegGPRC }, },
5845 { 6782 /* mfdec */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_22, AMFBS_None, { MCK_RegGPRC }, },
5846 { 6788 /* mfdscr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_17, AMFBS_None, { MCK_RegGPRC }, },
5847 { 6795 /* mfdsisr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_18, AMFBS_None, { MCK_RegGPRC }, },
5848 { 6803 /* mfesr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_980, AMFBS_None, { MCK_RegGPRC }, },
5859 { 6878 /* mfibatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_529, AMFBS_None, { MCK_RegGPRC, MCK_0 }, },
5860 { 6878 /* mfibatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_531, AMFBS_None, { MCK_RegGPRC, MCK_1 }, },
5861 { 6878 /* mfibatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_533, AMFBS_None, { MCK_RegGPRC, MCK_2 }, },
5862 { 6878 /* mfibatl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_535, AMFBS_None, { MCK_RegGPRC, MCK_3 }, },
5863 { 6886 /* mfibatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_528, AMFBS_None, { MCK_RegGPRC, MCK_0 }, },
5864 { 6886 /* mfibatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_530, AMFBS_None, { MCK_RegGPRC, MCK_1 }, },
5865 { 6886 /* mfibatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_532, AMFBS_None, { MCK_RegGPRC, MCK_2 }, },
5866 { 6886 /* mfibatu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_534, AMFBS_None, { MCK_RegGPRC, MCK_3 }, },
5867 { 6894 /* mficcr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_1019, AMFBS_None, { MCK_RegGPRC }, },
5871 { 6919 /* mfpid */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_48, AMFBS_None, { MCK_RegGPRC }, },
5873 { 6931 /* mfpvr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_287, AMFBS_None, { MCK_RegGPRC }, },
5874 { 6937 /* mfrtcl */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_5, AMFBS_None, { MCK_RegGPRC }, },
5875 { 6944 /* mfrtcu */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_4, AMFBS_None, { MCK_RegGPRC }, },
5876 { 6951 /* mfsdr1 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_25, AMFBS_None, { MCK_RegGPRC }, },
5877 { 6951 /* mfsdr1 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_25, AMFBS_None, { MCK_RegGPRC }, },
5878 { 6958 /* mfspefscr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_512, AMFBS_None, { MCK_RegGPRC }, },
5879 { 6968 /* mfspr */, PPC::MFSPR, Convert__RegGPRC1_0__Imm1_1, AMFBS_None, { MCK_RegGPRC, MCK_Imm }, },
5880 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_272, AMFBS_None, { MCK_RegGPRC, MCK_0 }, },
5881 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_273, AMFBS_None, { MCK_RegGPRC, MCK_1 }, },
5882 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_274, AMFBS_None, { MCK_RegGPRC, MCK_2 }, },
5883 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_275, AMFBS_None, { MCK_RegGPRC, MCK_3 }, },
5884 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_260, AMFBS_None, { MCK_RegGPRC, MCK_4 }, },
5885 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_261, AMFBS_None, { MCK_RegGPRC, MCK_5 }, },
5886 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_262, AMFBS_None, { MCK_RegGPRC, MCK_6 }, },
5887 { 6974 /* mfsprg */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_263, AMFBS_None, { MCK_RegGPRC, MCK_7 }, },
5888 { 6981 /* mfsprg0 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_272, AMFBS_None, { MCK_RegGPRC }, },
5889 { 6989 /* mfsprg1 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_273, AMFBS_None, { MCK_RegGPRC }, },
5890 { 6997 /* mfsprg2 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_274, AMFBS_None, { MCK_RegGPRC }, },
5891 { 7005 /* mfsprg3 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_275, AMFBS_None, { MCK_RegGPRC }, },
5892 { 7013 /* mfsprg4 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_260, AMFBS_None, { MCK_RegGPRC }, },
5893 { 7021 /* mfsprg5 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_261, AMFBS_None, { MCK_RegGPRC }, },
5894 { 7029 /* mfsprg6 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_262, AMFBS_None, { MCK_RegGPRC }, },
5895 { 7037 /* mfsprg7 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_263, AMFBS_None, { MCK_RegGPRC }, },
5898 { 7057 /* mfsrr0 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_26, AMFBS_None, { MCK_RegGPRC }, },
5899 { 7057 /* mfsrr0 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_26, AMFBS_None, { MCK_RegGPRC }, },
5900 { 7064 /* mfsrr1 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_27, AMFBS_None, { MCK_RegGPRC }, },
5901 { 7064 /* mfsrr1 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_27, AMFBS_None, { MCK_RegGPRC }, },
5902 { 7071 /* mfsrr2 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_990, AMFBS_None, { MCK_RegGPRC }, },
5903 { 7078 /* mfsrr3 */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_991, AMFBS_None, { MCK_RegGPRC }, },
5906 { 7090 /* mftbhi */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_988, AMFBS_None, { MCK_RegGPRC }, },
5908 { 7103 /* mftblo */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_989, AMFBS_None, { MCK_RegGPRC }, },
5910 { 7116 /* mftcr */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_986, AMFBS_None, { MCK_RegGPRC }, },
5918 { 7174 /* mfxer */, PPC::MFSPR, Convert__RegGPRC1_0__imm_95_1, AMFBS_None, { MCK_RegGPRC }, },
gen/lib/Target/PowerPC/PPCGenAsmWriter.inc 8822 case PPC::MFSPR:
gen/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc 5037 case PPC::MFSPR:
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 1101 Inst.setOpcode(PPC::MFSPR);
lib/Target/PowerPC/PPCISelLowering.cpp11028 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
11029 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
11030 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);