|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 3161 { 253, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #253 = ADD4o
3165 { 257, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #257 = ADD8o
3212 { 304, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #304 = AND8o
3215 { 307, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #307 = ANDC8o
3216 { 308, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #308 = ANDCo
3217 { 309, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr }, // Inst #309 = ANDISo
3218 { 310, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo39, -1 ,nullptr }, // Inst #310 = ANDISo8
3219 { 311, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr }, // Inst #311 = ANDIo
3220 { 312, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo39, -1 ,nullptr }, // Inst #312 = ANDIo8
3225 { 317, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #317 = ANDo
3226 { 318, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo63, -1 ,nullptr }, // Inst #318 = ATOMIC_CMP_SWAP_I16
3227 { 319, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo63, -1 ,nullptr }, // Inst #319 = ATOMIC_CMP_SWAP_I32
3228 { 320, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo64, -1 ,nullptr }, // Inst #320 = ATOMIC_CMP_SWAP_I64
3229 { 321, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo63, -1 ,nullptr }, // Inst #321 = ATOMIC_CMP_SWAP_I8
3230 { 322, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #322 = ATOMIC_LOAD_ADD_I16
3231 { 323, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #323 = ATOMIC_LOAD_ADD_I32
3232 { 324, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #324 = ATOMIC_LOAD_ADD_I64
3233 { 325, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #325 = ATOMIC_LOAD_ADD_I8
3234 { 326, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #326 = ATOMIC_LOAD_AND_I16
3235 { 327, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #327 = ATOMIC_LOAD_AND_I32
3236 { 328, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #328 = ATOMIC_LOAD_AND_I64
3237 { 329, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #329 = ATOMIC_LOAD_AND_I8
3238 { 330, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #330 = ATOMIC_LOAD_MAX_I16
3239 { 331, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #331 = ATOMIC_LOAD_MAX_I32
3240 { 332, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #332 = ATOMIC_LOAD_MAX_I64
3241 { 333, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #333 = ATOMIC_LOAD_MAX_I8
3242 { 334, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #334 = ATOMIC_LOAD_MIN_I16
3243 { 335, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #335 = ATOMIC_LOAD_MIN_I32
3244 { 336, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #336 = ATOMIC_LOAD_MIN_I64
3245 { 337, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #337 = ATOMIC_LOAD_MIN_I8
3246 { 338, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #338 = ATOMIC_LOAD_NAND_I16
3247 { 339, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #339 = ATOMIC_LOAD_NAND_I32
3248 { 340, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #340 = ATOMIC_LOAD_NAND_I64
3249 { 341, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #341 = ATOMIC_LOAD_NAND_I8
3250 { 342, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #342 = ATOMIC_LOAD_OR_I16
3251 { 343, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #343 = ATOMIC_LOAD_OR_I32
3252 { 344, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #344 = ATOMIC_LOAD_OR_I64
3253 { 345, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #345 = ATOMIC_LOAD_OR_I8
3254 { 346, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #346 = ATOMIC_LOAD_SUB_I16
3255 { 347, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #347 = ATOMIC_LOAD_SUB_I32
3256 { 348, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #348 = ATOMIC_LOAD_SUB_I64
3257 { 349, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #349 = ATOMIC_LOAD_SUB_I8
3258 { 350, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #350 = ATOMIC_LOAD_UMAX_I16
3259 { 351, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #351 = ATOMIC_LOAD_UMAX_I32
3260 { 352, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #352 = ATOMIC_LOAD_UMAX_I64
3261 { 353, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #353 = ATOMIC_LOAD_UMAX_I8
3262 { 354, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #354 = ATOMIC_LOAD_UMIN_I16
3263 { 355, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #355 = ATOMIC_LOAD_UMIN_I32
3264 { 356, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #356 = ATOMIC_LOAD_UMIN_I64
3265 { 357, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #357 = ATOMIC_LOAD_UMIN_I8
3266 { 358, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #358 = ATOMIC_LOAD_XOR_I16
3267 { 359, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #359 = ATOMIC_LOAD_XOR_I32
3268 { 360, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #360 = ATOMIC_LOAD_XOR_I64
3269 { 361, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #361 = ATOMIC_LOAD_XOR_I8
3270 { 362, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #362 = ATOMIC_SWAP_I16
3271 { 363, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #363 = ATOMIC_SWAP_I32
3272 { 364, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo66, -1 ,nullptr }, // Inst #364 = ATOMIC_SWAP_I64
3273 { 365, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList3, OperandInfo65, -1 ,nullptr }, // Inst #365 = ATOMIC_SWAP_I8
3393 { 485, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #485 = CNTLZDo
3396 { 488, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #488 = CNTLZW8o
3397 { 489, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #489 = CNTLZWo
3399 { 491, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #491 = CNTTZDo
3402 { 494, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #494 = CNTTZW8o
3403 { 495, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #495 = CNTTZWo
3410 { 502, 3, 0, 4, 203, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo40, -1 ,nullptr }, // Inst #502 = CP_PASTEo
3443 { 535, 3, 1, 4, 243, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #535 = DIVDEUo
3444 { 536, 3, 1, 4, 243, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #536 = DIVDEo
3446 { 538, 3, 1, 4, 241, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #538 = DIVDUo
3447 { 539, 3, 1, 4, 241, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #539 = DIVDo
3451 { 543, 3, 1, 4, 242, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #543 = DIVWEUo
3452 { 544, 3, 1, 4, 242, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #544 = DIVWEo
3454 { 546, 3, 1, 4, 240, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #546 = DIVWUo
3455 { 547, 3, 1, 4, 240, 0, 0xdULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #547 = DIVWo
3529 { 621, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #621 = EQV8o
3530 { 622, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #622 = EQVo
3729 { 821, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #821 = EXTSB8o
3730 { 822, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #822 = EXTSBo
3734 { 826, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #826 = EXTSH8o
3735 { 827, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #827 = EXTSHo
3739 { 831, 3, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo105, -1 ,nullptr }, // Inst #831 = EXTSWSLI_32_64o
3743 { 835, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo104, -1 ,nullptr }, // Inst #835 = EXTSW_32_64o
3744 { 836, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #836 = EXTSWo
4087 { 1179, 3, 1, 4, 153, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1179 = MULHDUo
4088 { 1180, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1180 = MULHDo
4091 { 1183, 3, 1, 4, 153, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1183 = MULHWUo
4092 { 1184, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1184 = MULHWo
4094 { 1186, 3, 1, 4, 155, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1186 = MULLDo
4098 { 1190, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1190 = MULLWo
4104 { 1196, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1196 = NAND8o
4105 { 1197, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1197 = NANDo
4109 { 1201, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo59, -1 ,nullptr }, // Inst #1201 = NEG8o
4110 { 1202, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #1202 = NEGo
4116 { 1208, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1208 = NOR8o
4117 { 1209, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1209 = NORo
4120 { 1212, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1212 = OR8o
4123 { 1215, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1215 = ORC8o
4124 { 1216, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1216 = ORCo
4129 { 1221, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1221 = ORo
4312 { 1404, 4, 1, 4, 250, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo206, -1 ,nullptr }, // Inst #1404 = RLDCLo
4314 { 1406, 4, 1, 4, 250, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo206, -1 ,nullptr }, // Inst #1406 = RLDCRo
4319 { 1411, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1411 = RLDICL_32o
4320 { 1412, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #1412 = RLDICLo
4323 { 1415, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #1415 = RLDICRo
4324 { 1416, 4, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #1416 = RLDICo
4326 { 1418, 5, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo208, -1 ,nullptr }, // Inst #1418 = RLDIMIo
4329 { 1421, 6, 1, 4, 252, 0, 0xcULL, nullptr, ImplicitList3, OperandInfo210, -1 ,nullptr }, // Inst #1421 = RLWIMI8o
4330 { 1422, 6, 1, 4, 252, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList3, OperandInfo209, -1 ,nullptr }, // Inst #1422 = RLWIMIo
4333 { 1425, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo212, -1 ,nullptr }, // Inst #1425 = RLWINM8o
4334 { 1426, 5, 1, 4, 253, 0, 0xcULL, nullptr, ImplicitList3, OperandInfo211, -1 ,nullptr }, // Inst #1426 = RLWINMo
4337 { 1429, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo214, -1 ,nullptr }, // Inst #1429 = RLWNM8o
4338 { 1430, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo213, -1 ,nullptr }, // Inst #1430 = RLWNMo
4373 { 1465, 2, 1, 4, 312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #1465 = SLBFEEo
4382 { 1474, 3, 1, 4, 258, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo240, -1 ,nullptr }, // Inst #1474 = SLDo
4385 { 1477, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1477 = SLW8o
4386 { 1478, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1478 = SLWo
4404 { 1496, 3, 1, 4, 258, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo240, -1 ,nullptr }, // Inst #1496 = SRDo
4407 { 1499, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1499 = SRW8o
4408 { 1500, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1500 = SRWo
4412 { 1504, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList3, OperandInfo119, -1 ,nullptr }, // Inst #1504 = STBCX
4427 { 1519, 3, 0, 4, 200, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList3, OperandInfo125, -1 ,nullptr }, // Inst #1519 = STDCX
4447 { 1539, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList3, OperandInfo119, -1 ,nullptr }, // Inst #1539 = STHCX
4471 { 1563, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList3, OperandInfo119, -1 ,nullptr }, // Inst #1563 = STWCX
4501 { 1593, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1593 = SUBF8o
4520 { 1612, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1612 = SUBFo
4522 { 1614, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo151, -1 ,nullptr }, // Inst #1614 = TABORT
4523 { 1615, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo85, -1 ,nullptr }, // Inst #1615 = TABORTDC
4524 { 1616, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo249, -1 ,nullptr }, // Inst #1616 = TABORTDCI
4525 { 1617, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo85, -1 ,nullptr }, // Inst #1617 = TABORTWC
4526 { 1618, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo249, -1 ,nullptr }, // Inst #1618 = TABORTWCI
4533 { 1625, 1, 0, 4, 122, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1625 = TBEGIN
4545 { 1637, 1, 0, 4, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1637 = TEND
4561 { 1653, 0, 0, 4, 122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr }, // Inst #1653 = TRECHKPT
4562 { 1654, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo151, -1 ,nullptr }, // Inst #1654 = TRECLAIM
4563 { 1655, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1655 = TSR
4864 { 1956, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo54, -1 ,nullptr }, // Inst #1956 = XOR8o
4869 { 1961, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo53, -1 ,nullptr }, // Inst #1961 = XORo