|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 3156 { 248, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #248 = XFLOADf64
3158 { 250, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #250 = XFSTOREf64
3284 { 376, 3, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo68, -1 ,nullptr }, // Inst #376 = BCCL
3285 { 377, 3, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo68, -1 ,nullptr }, // Inst #377 = BCCLA
3309 { 401, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo67, -1 ,nullptr }, // Inst #401 = BCL
3314 { 406, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #406 = BCLalways
3315 { 407, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo67, -1 ,nullptr }, // Inst #407 = BCLn
3362 { 454, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo76, -1 ,nullptr }, // Inst #454 = BL
3363 { 455, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo76, -1 ,nullptr }, // Inst #455 = BL8
3364 { 456, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo76, -1 ,nullptr }, // Inst #456 = BL8_NOP
3365 { 457, 2, 0, 8, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo7, -1 ,nullptr }, // Inst #457 = BL8_NOP_TLS
3366 { 458, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo7, -1 ,nullptr }, // Inst #458 = BL8_TLS
3367 { 459, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo7, -1 ,nullptr }, // Inst #459 = BL8_TLS_
3368 { 460, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #460 = BLA
3369 { 461, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo2, -1 ,nullptr }, // Inst #461 = BLA8
3370 { 462, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList14, OperandInfo2, -1 ,nullptr }, // Inst #462 = BLA8_NOP
3374 { 466, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo76, -1 ,nullptr }, // Inst #466 = BL_NOP
3375 { 467, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, ImplicitList12, OperandInfo7, -1 ,nullptr }, // Inst #467 = BL_TLS
3750 { 842, 3, 1, 4, 149, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #842 = FADD
3751 { 843, 3, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #843 = FADDS
3752 { 844, 3, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo109, -1 ,nullptr }, // Inst #844 = FADDSo
3753 { 845, 3, 1, 4, 157, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo108, -1 ,nullptr }, // Inst #845 = FADDo
3754 { 846, 3, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #846 = FADDrtz
3755 { 847, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #847 = FCFID
3756 { 848, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #848 = FCFIDS
3757 { 849, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo110, -1 ,nullptr }, // Inst #849 = FCFIDSo
3758 { 850, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #850 = FCFIDU
3759 { 851, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #851 = FCFIDUS
3760 { 852, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo110, -1 ,nullptr }, // Inst #852 = FCFIDUSo
3761 { 853, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #853 = FCFIDUo
3762 { 854, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #854 = FCFIDo
3769 { 861, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #861 = FCTID
3770 { 862, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #862 = FCTIDU
3771 { 863, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #863 = FCTIDUZ
3772 { 864, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #864 = FCTIDUZo
3773 { 865, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #865 = FCTIDUo
3774 { 866, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #866 = FCTIDZ
3775 { 867, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #867 = FCTIDZo
3776 { 868, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #868 = FCTIDo
3777 { 869, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #869 = FCTIW
3778 { 870, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #870 = FCTIWU
3779 { 871, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #871 = FCTIWUZ
3780 { 872, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #872 = FCTIWUZo
3781 { 873, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #873 = FCTIWUo
3782 { 874, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #874 = FCTIWZ
3783 { 875, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #875 = FCTIWZo
3784 { 876, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #876 = FCTIWo
3785 { 877, 3, 1, 4, 259, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #877 = FDIV
3786 { 878, 3, 1, 4, 270, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #878 = FDIVS
3787 { 879, 3, 1, 4, 271, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo109, -1 ,nullptr }, // Inst #879 = FDIVSo
3788 { 880, 3, 1, 4, 260, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo108, -1 ,nullptr }, // Inst #880 = FDIVo
3789 { 881, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #881 = FMADD
3790 { 882, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #882 = FMADDS
3791 { 883, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo114, -1 ,nullptr }, // Inst #883 = FMADDSo
3792 { 884, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo113, -1 ,nullptr }, // Inst #884 = FMADDo
3795 { 887, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #887 = FMSUB
3796 { 888, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #888 = FMSUBS
3797 { 889, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo114, -1 ,nullptr }, // Inst #889 = FMSUBSo
3798 { 890, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo113, -1 ,nullptr }, // Inst #890 = FMSUBo
3799 { 891, 3, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #891 = FMUL
3800 { 892, 3, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #892 = FMULS
3801 { 893, 3, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo109, -1 ,nullptr }, // Inst #893 = FMULSo
3802 { 894, 3, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo108, -1 ,nullptr }, // Inst #894 = FMULo
3811 { 903, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #903 = FNMADD
3812 { 904, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #904 = FNMADDS
3813 { 905, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo114, -1 ,nullptr }, // Inst #905 = FNMADDSo
3814 { 906, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo113, -1 ,nullptr }, // Inst #906 = FNMADDo
3815 { 907, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #907 = FNMSUB
3816 { 908, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #908 = FNMSUBS
3817 { 909, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo114, -1 ,nullptr }, // Inst #909 = FNMSUBSo
3818 { 910, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo113, -1 ,nullptr }, // Inst #910 = FNMSUBo
3823 { 915, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #915 = FRIMD
3824 { 916, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #916 = FRIMDo
3825 { 917, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #917 = FRIMS
3826 { 918, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo107, -1 ,nullptr }, // Inst #918 = FRIMSo
3827 { 919, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #919 = FRIND
3828 { 920, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #920 = FRINDo
3829 { 921, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #921 = FRINS
3830 { 922, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo107, -1 ,nullptr }, // Inst #922 = FRINSo
3831 { 923, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #923 = FRIPD
3832 { 924, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #924 = FRIPDo
3833 { 925, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #925 = FRIPS
3834 { 926, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo107, -1 ,nullptr }, // Inst #926 = FRIPSo
3835 { 927, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #927 = FRIZD
3836 { 928, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #928 = FRIZDo
3837 { 929, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #929 = FRIZS
3838 { 930, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo107, -1 ,nullptr }, // Inst #930 = FRIZSo
3839 { 931, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #931 = FRSP
3840 { 932, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo110, -1 ,nullptr }, // Inst #932 = FRSPo
3849 { 941, 2, 1, 4, 262, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #941 = FSQRT
3850 { 942, 2, 1, 4, 267, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #942 = FSQRTS
3851 { 943, 2, 1, 4, 268, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo107, -1 ,nullptr }, // Inst #943 = FSQRTSo
3852 { 944, 2, 1, 4, 265, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo106, -1 ,nullptr }, // Inst #944 = FSQRTo
3853 { 945, 3, 1, 4, 149, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #945 = FSUB
3854 { 946, 3, 1, 4, 148, 0, 0x18ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #946 = FSUBS
3855 { 947, 3, 1, 4, 156, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo109, -1 ,nullptr }, // Inst #947 = FSUBSo
3856 { 948, 3, 1, 4, 157, 0, 0x18ULL, ImplicitList2, ImplicitList23, OperandInfo108, -1 ,nullptr }, // Inst #948 = FSUBo
3984 { 1076, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1076 = LXSDX
3993 { 1085, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1085 = LXVD2X
3994 { 1086, 3, 1, 4, 214, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1086 = LXVDSX
3998 { 1090, 3, 1, 4, 214, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1090 = LXVW4X
4015 { 1107, 1, 1, 4, 255, 0, 0x1aULL, ImplicitList2, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1107 = MFFS
4016 { 1108, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #1108 = MFFSCDRN
4017 { 1109, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1109 = MFFSCDRNI
4018 { 1110, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1110 = MFFSCE
4019 { 1111, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #1111 = MFFSCRN
4020 { 1112, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1112 = MFFSCRNI
4021 { 1113, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1113 = MFFSL
4022 { 1114, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList23, OperandInfo153, -1 ,nullptr }, // Inst #1114 = MFFSo
4056 { 1148, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1148 = MTFSB0
4056 { 1148, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1148 = MTFSB0
4057 { 1149, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1149 = MTFSB1
4057 { 1149, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1149 = MTFSB1
4061 { 1153, 2, 0, 4, 249, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #1153 = MTFSFb
4061 { 1153, 2, 0, 4, 249, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList2, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #1153 = MTFSFb
4135 { 1227, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1227 = QVALIGNI
4136 { 1228, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1228 = QVALIGNIb
4137 { 1229, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1229 = QVALIGNIs
4138 { 1230, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1230 = QVESPLATI
4139 { 1231, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1231 = QVESPLATIb
4140 { 1232, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1232 = QVESPLATIs
4141 { 1233, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1233 = QVFABS
4142 { 1234, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1234 = QVFABSs
4143 { 1235, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1235 = QVFADD
4144 { 1236, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1236 = QVFADDS
4145 { 1237, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1237 = QVFADDSs
4146 { 1238, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1238 = QVFCFID
4147 { 1239, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1239 = QVFCFIDS
4148 { 1240, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1240 = QVFCFIDU
4149 { 1241, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1241 = QVFCFIDUS
4150 { 1242, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1242 = QVFCFIDb
4151 { 1243, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1243 = QVFCMPEQ
4152 { 1244, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1244 = QVFCMPEQb
4153 { 1245, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1245 = QVFCMPEQbs
4154 { 1246, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1246 = QVFCMPGT
4155 { 1247, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1247 = QVFCMPGTb
4156 { 1248, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1248 = QVFCMPGTbs
4157 { 1249, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1249 = QVFCMPLT
4158 { 1250, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1250 = QVFCMPLTb
4159 { 1251, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1251 = QVFCMPLTbs
4160 { 1252, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1252 = QVFCPSGN
4161 { 1253, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1253 = QVFCPSGNs
4162 { 1254, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1254 = QVFCTID
4163 { 1255, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1255 = QVFCTIDU
4164 { 1256, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1256 = QVFCTIDUZ
4165 { 1257, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1257 = QVFCTIDZ
4166 { 1258, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1258 = QVFCTIDb
4167 { 1259, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1259 = QVFCTIW
4168 { 1260, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1260 = QVFCTIWU
4169 { 1261, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1261 = QVFCTIWUZ
4170 { 1262, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1262 = QVFCTIWZ
4171 { 1263, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1263 = QVFLOGICAL
4172 { 1264, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1264 = QVFLOGICALb
4173 { 1265, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1265 = QVFLOGICALs
4174 { 1266, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1266 = QVFMADD
4175 { 1267, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1267 = QVFMADDS
4176 { 1268, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1268 = QVFMADDSs
4177 { 1269, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1269 = QVFMR
4178 { 1270, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1270 = QVFMRb
4179 { 1271, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1271 = QVFMRs
4180 { 1272, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1272 = QVFMSUB
4181 { 1273, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1273 = QVFMSUBS
4182 { 1274, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1274 = QVFMSUBSs
4183 { 1275, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1275 = QVFMUL
4184 { 1276, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1276 = QVFMULS
4185 { 1277, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1277 = QVFMULSs
4186 { 1278, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1278 = QVFNABS
4187 { 1279, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1279 = QVFNABSs
4188 { 1280, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1280 = QVFNEG
4189 { 1281, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1281 = QVFNEGs
4190 { 1282, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1282 = QVFNMADD
4191 { 1283, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1283 = QVFNMADDS
4192 { 1284, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1284 = QVFNMADDSs
4193 { 1285, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1285 = QVFNMSUB
4194 { 1286, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1286 = QVFNMSUBS
4195 { 1287, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1287 = QVFNMSUBSs
4196 { 1288, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1288 = QVFPERM
4197 { 1289, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1289 = QVFPERMs
4198 { 1290, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1290 = QVFRE
4199 { 1291, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1291 = QVFRES
4200 { 1292, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1292 = QVFRESs
4201 { 1293, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1293 = QVFRIM
4202 { 1294, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1294 = QVFRIMs
4203 { 1295, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1295 = QVFRIN
4204 { 1296, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1296 = QVFRINs
4205 { 1297, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1297 = QVFRIP
4206 { 1298, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1298 = QVFRIPs
4207 { 1299, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1299 = QVFRIZ
4208 { 1300, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1300 = QVFRIZs
4209 { 1301, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1301 = QVFRSP
4210 { 1302, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1302 = QVFRSPs
4211 { 1303, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1303 = QVFRSQRTE
4212 { 1304, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1304 = QVFRSQRTES
4213 { 1305, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1305 = QVFRSQRTESs
4214 { 1306, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1306 = QVFSEL
4215 { 1307, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1307 = QVFSELb
4216 { 1308, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1308 = QVFSELbb
4217 { 1309, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1309 = QVFSELbs
4218 { 1310, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1310 = QVFSUB
4219 { 1311, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1311 = QVFSUBS
4220 { 1312, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1312 = QVFSUBSs
4221 { 1313, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1313 = QVFTSTNAN
4222 { 1314, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1314 = QVFTSTNANb
4223 { 1315, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1315 = QVFTSTNANbs
4224 { 1316, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1316 = QVFXMADD
4225 { 1317, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1317 = QVFXMADDS
4226 { 1318, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1318 = QVFXMUL
4227 { 1319, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1319 = QVFXMULS
4228 { 1320, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1320 = QVFXXCPNMADD
4229 { 1321, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1321 = QVFXXCPNMADDS
4230 { 1322, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1322 = QVFXXMADD
4231 { 1323, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1323 = QVFXXMADDS
4232 { 1324, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1324 = QVFXXNPMADD
4233 { 1325, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1325 = QVFXXNPMADDS
4234 { 1326, 2, 1, 4, 68, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList2, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1326 = QVGPCI
4235 { 1327, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1327 = QVLFCDUX
4236 { 1328, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1328 = QVLFCDUXA
4237 { 1329, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1329 = QVLFCDX
4238 { 1330, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1330 = QVLFCDXA
4239 { 1331, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1331 = QVLFCSUX
4240 { 1332, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1332 = QVLFCSUXA
4241 { 1333, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1333 = QVLFCSX
4242 { 1334, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1334 = QVLFCSXA
4243 { 1335, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1335 = QVLFCSXs
4244 { 1336, 4, 2, 4, 40, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1336 = QVLFDUX
4245 { 1337, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1337 = QVLFDUXA
4246 { 1338, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1338 = QVLFDX
4247 { 1339, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1339 = QVLFDXA
4248 { 1340, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1340 = QVLFDXb
4249 { 1341, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1341 = QVLFIWAX
4250 { 1342, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1342 = QVLFIWAXA
4251 { 1343, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1343 = QVLFIWZX
4252 { 1344, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1344 = QVLFIWZXA
4253 { 1345, 4, 2, 4, 40, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1345 = QVLFSUX
4254 { 1346, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1346 = QVLFSUXA
4255 { 1347, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1347 = QVLFSX
4256 { 1348, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1348 = QVLFSXA
4257 { 1349, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList2, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1349 = QVLFSXb
4258 { 1350, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1350 = QVLFSXs
4259 { 1351, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1351 = QVLPCLDX
4260 { 1352, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1352 = QVLPCLSX
4261 { 1353, 2, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1353 = QVLPCLSXint
4262 { 1354, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1354 = QVLPCRDX
4263 { 1355, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1355 = QVLPCRSX
4264 { 1356, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1356 = QVSTFCDUX
4265 { 1357, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1357 = QVSTFCDUXA
4266 { 1358, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1358 = QVSTFCDUXI
4267 { 1359, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1359 = QVSTFCDUXIA
4268 { 1360, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1360 = QVSTFCDX
4269 { 1361, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1361 = QVSTFCDXA
4270 { 1362, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1362 = QVSTFCDXI
4271 { 1363, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1363 = QVSTFCDXIA
4272 { 1364, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1364 = QVSTFCSUX
4273 { 1365, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1365 = QVSTFCSUXA
4274 { 1366, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1366 = QVSTFCSUXI
4275 { 1367, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1367 = QVSTFCSUXIA
4276 { 1368, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1368 = QVSTFCSX
4277 { 1369, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1369 = QVSTFCSXA
4278 { 1370, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1370 = QVSTFCSXI
4279 { 1371, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1371 = QVSTFCSXIA
4280 { 1372, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1372 = QVSTFCSXs
4281 { 1373, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1373 = QVSTFDUX
4282 { 1374, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1374 = QVSTFDUXA
4283 { 1375, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1375 = QVSTFDUXI
4284 { 1376, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1376 = QVSTFDUXIA
4285 { 1377, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1377 = QVSTFDX
4286 { 1378, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1378 = QVSTFDXA
4287 { 1379, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1379 = QVSTFDXI
4288 { 1380, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1380 = QVSTFDXIA
4289 { 1381, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1381 = QVSTFDXb
4290 { 1382, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1382 = QVSTFIWX
4291 { 1383, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1383 = QVSTFIWXA
4292 { 1384, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1384 = QVSTFSUX
4293 { 1385, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1385 = QVSTFSUXA
4294 { 1386, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1386 = QVSTFSUXI
4295 { 1387, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1387 = QVSTFSUXIA
4296 { 1388, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1388 = QVSTFSUXs
4297 { 1389, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1389 = QVSTFSX
4298 { 1390, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1390 = QVSTFSXA
4299 { 1391, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1391 = QVSTFSXI
4300 { 1392, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList2, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1392 = QVSTFSXIA
4301 { 1393, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1393 = QVSTFSXs
4346 { 1438, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1438 = SELECT_CC_QBRC
4347 { 1439, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1439 = SELECT_CC_QFRC
4348 { 1440, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1440 = SELECT_CC_QSRC
4360 { 1452, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1452 = SELECT_QBRC
4361 { 1453, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1453 = SELECT_QFRC
4362 { 1454, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1454 = SELECT_QSRC
4371 { 1463, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo239, -1 ,nullptr }, // Inst #1463 = SETRND
4371 { 1463, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo239, -1 ,nullptr }, // Inst #1463 = SETRND
4372 { 1464, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo154, -1 ,nullptr }, // Inst #1464 = SETRNDi
4372 { 1464, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo154, -1 ,nullptr }, // Inst #1464 = SETRNDi
4483 { 1575, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1575 = STXSDX
4493 { 1585, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1585 = STXVD2X
4497 { 1589, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1589 = STXVW4X
4527 { 1619, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1619 = TAILB
4528 { 1620, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1620 = TAILB8
4529 { 1621, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = TAILBA
4530 { 1622, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1622 = TAILBA8
4537 { 1629, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1629 = TCRETURNai
4538 { 1630, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1630 = TCRETURNai8
4539 { 1631, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1631 = TCRETURNdi
4540 { 1632, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1632 = TCRETURNdi8
4541 { 1633, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1633 = TCRETURNri
4542 { 1634, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1634 = TCRETURNri8
4870 { 1962, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1962 = XSABSDP
4872 { 1964, 3, 1, 4, 159, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1964 = XSADDDP
4881 { 1973, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1973 = XSCMPODP
4883 { 1975, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1975 = XSCMPUDP
4885 { 1977, 3, 1, 4, 120, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1977 = XSCPSGNDP
4889 { 1981, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1981 = XSCVDPSP
4891 { 1983, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1983 = XSCVDPSXDS
4892 { 1984, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1984 = XSCVDPSXDSs
4893 { 1985, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1985 = XSCVDPSXWS
4894 { 1986, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1986 = XSCVDPSXWSs
4895 { 1987, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1987 = XSCVDPUXDS
4896 { 1988, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1988 = XSCVDPUXDSs
4897 { 1989, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1989 = XSCVDPUXWS
4898 { 1990, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1990 = XSCVDPUXWSs
4907 { 1999, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1999 = XSCVSPDP
4909 { 2001, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2001 = XSCVSXDDP
4912 { 2004, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2004 = XSCVUXDDP
4914 { 2006, 3, 1, 4, 269, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2006 = XSDIVDP
4920 { 2012, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2012 = XSMADDADP
4922 { 2014, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2014 = XSMADDMDP
4927 { 2019, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2019 = XSMAXDP
4930 { 2022, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2022 = XSMINDP
4932 { 2024, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2024 = XSMSUBADP
4934 { 2026, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2026 = XSMSUBMDP
4938 { 2030, 3, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2030 = XSMULDP
4942 { 2034, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2034 = XSNABSDP
4944 { 2036, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2036 = XSNEGDP
4946 { 2038, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2038 = XSNMADDADP
4948 { 2040, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2040 = XSNMADDMDP
4952 { 2044, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2044 = XSNMSUBADP
4954 { 2046, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2046 = XSNMSUBMDP
4958 { 2050, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2050 = XSRDPI
4959 { 2051, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2051 = XSRDPIC
4960 { 2052, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2052 = XSRDPIM
4961 { 2053, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2053 = XSRDPIP
4962 { 2054, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2054 = XSRDPIZ
4963 { 2055, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2055 = XSREDP
4969 { 2061, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2061 = XSRSQRTEDP
4971 { 2063, 2, 1, 4, 261, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2063 = XSSQRTDP
4975 { 2067, 3, 1, 4, 159, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2067 = XSSUBDP
4979 { 2071, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2071 = XSTDIVDP
4980 { 2072, 2, 1, 4, 109, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2072 = XSTSQRTDP
4988 { 2080, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2080 = XVABSDP
4989 { 2081, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2081 = XVABSSP
4990 { 2082, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2082 = XVADDDP
4991 { 2083, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2083 = XVADDSP
4992 { 2084, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2084 = XVCMPEQDP
4993 { 2085, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2085 = XVCMPEQDPo
4994 { 2086, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2086 = XVCMPEQSP
4995 { 2087, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2087 = XVCMPEQSPo
4996 { 2088, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2088 = XVCMPGEDP
4997 { 2089, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2089 = XVCMPGEDPo
4998 { 2090, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2090 = XVCMPGESP
4999 { 2091, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2091 = XVCMPGESPo
5000 { 2092, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2092 = XVCMPGTDP
5001 { 2093, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2093 = XVCMPGTDPo
5002 { 2094, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2094 = XVCMPGTSP
5003 { 2095, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList2, ImplicitList16, OperandInfo289, -1 ,nullptr }, // Inst #2095 = XVCMPGTSPo
5004 { 2096, 3, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2096 = XVCPSGNDP
5005 { 2097, 3, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2097 = XVCPSGNSP
5006 { 2098, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2098 = XVCVDPSP
5007 { 2099, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2099 = XVCVDPSXDS
5008 { 2100, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2100 = XVCVDPSXWS
5009 { 2101, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2101 = XVCVDPUXDS
5010 { 2102, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2102 = XVCVDPUXWS
5012 { 2104, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2104 = XVCVSPDP
5014 { 2106, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2106 = XVCVSPSXDS
5015 { 2107, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2107 = XVCVSPSXWS
5016 { 2108, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2108 = XVCVSPUXDS
5017 { 2109, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2109 = XVCVSPUXWS
5018 { 2110, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2110 = XVCVSXDDP
5019 { 2111, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2111 = XVCVSXDSP
5020 { 2112, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2112 = XVCVSXWDP
5021 { 2113, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2113 = XVCVSXWSP
5022 { 2114, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2114 = XVCVUXDDP
5023 { 2115, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2115 = XVCVUXDSP
5024 { 2116, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2116 = XVCVUXWDP
5025 { 2117, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2117 = XVCVUXWSP
5026 { 2118, 3, 1, 4, 274, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2118 = XVDIVDP
5027 { 2119, 3, 1, 4, 273, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2119 = XVDIVSP
5030 { 2122, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2122 = XVMADDADP
5031 { 2123, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2123 = XVMADDASP
5032 { 2124, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2124 = XVMADDMDP
5033 { 2125, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2125 = XVMADDMSP
5034 { 2126, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2126 = XVMAXDP
5035 { 2127, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2127 = XVMAXSP
5036 { 2128, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2128 = XVMINDP
5037 { 2129, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2129 = XVMINSP
5038 { 2130, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2130 = XVMSUBADP
5039 { 2131, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2131 = XVMSUBASP
5040 { 2132, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2132 = XVMSUBMDP
5041 { 2133, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2133 = XVMSUBMSP
5042 { 2134, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2134 = XVMULDP
5043 { 2135, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2135 = XVMULSP
5044 { 2136, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2136 = XVNABSDP
5045 { 2137, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2137 = XVNABSSP
5046 { 2138, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2138 = XVNEGDP
5047 { 2139, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2139 = XVNEGSP
5048 { 2140, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2140 = XVNMADDADP
5049 { 2141, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2141 = XVNMADDASP
5050 { 2142, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2142 = XVNMADDMDP
5051 { 2143, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2143 = XVNMADDMSP
5052 { 2144, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2144 = XVNMSUBADP
5053 { 2145, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2145 = XVNMSUBASP
5054 { 2146, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2146 = XVNMSUBMDP
5055 { 2147, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2147 = XVNMSUBMSP
5056 { 2148, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2148 = XVRDPI
5057 { 2149, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2149 = XVRDPIC
5058 { 2150, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2150 = XVRDPIM
5059 { 2151, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2151 = XVRDPIP
5060 { 2152, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2152 = XVRDPIZ
5061 { 2153, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2153 = XVREDP
5062 { 2154, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2154 = XVRESP
5063 { 2155, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2155 = XVRSPI
5064 { 2156, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2156 = XVRSPIC
5065 { 2157, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2157 = XVRSPIM
5066 { 2158, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2158 = XVRSPIP
5067 { 2159, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2159 = XVRSPIZ
5068 { 2160, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2160 = XVRSQRTEDP
5069 { 2161, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2161 = XVRSQRTESP
5070 { 2162, 2, 1, 4, 263, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2162 = XVSQRTDP
5071 { 2163, 2, 1, 4, 264, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2163 = XVSQRTSP
5072 { 2164, 3, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2164 = XVSUBDP
5073 { 2165, 3, 1, 4, 142, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2165 = XVSUBSP
5074 { 2166, 3, 1, 4, 141, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2166 = XVTDIVDP
5075 { 2167, 3, 1, 4, 141, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2167 = XVTDIVSP
5076 { 2168, 2, 1, 4, 141, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2168 = XVTSQRTDP
5077 { 2169, 2, 1, 4, 141, 0, 0x0ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2169 = XVTSQRTSP