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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 923 { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
927 { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
931 { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
935 { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_Done },
939 { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_Done },
943 { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_Done },
959 { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
963 { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
967 { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
971 { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_Done },
975 { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_Done },
979 { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_Done },
983 { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
987 { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
991 { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
995 { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_Done },
999 { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_Done },
1003 { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_Done },
1009 { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1013 { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1017 { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1021 { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_Done },
1025 { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_Done },
1029 { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_Done },
1033 { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1037 { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1041 { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1045 { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_Done },
1049 { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_Done },
1053 { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_Done },
1057 { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1061 { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1065 { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1069 { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_Done },
1073 { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_Done },
1077 { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_Done },
1081 { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1085 { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1089 { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1093 { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_Done },
1097 { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_Done },
1101 { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_Done },
1107 { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1111 { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1115 { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1119 { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_Done },
1123 { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_Done },
1127 { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_Done },
1173 { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1177 { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1187 { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done },
1195 { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1199 { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done },
1205 { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
2149 case CVT_regCR0:
2574 case CVT_regCR0: