|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc10699 { 4068, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4068 = anonymous_6034
10700 { 4069, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4069 = anonymous_6036
10702 { 4071, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4071 = anonymous_6040
10703 { 4072, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4072 = anonymous_6042
10716 { 4085, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4085 = anonymous_6068
10717 { 4086, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4086 = anonymous_6070
10718 { 4087, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4087 = anonymous_6072
10914 { 4283, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4283 = anonymous_6507
10915 { 4284, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4284 = anonymous_6509
10917 { 4286, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4286 = anonymous_6513
10918 { 4287, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4287 = anonymous_6515
10931 { 4300, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4300 = anonymous_6541
10932 { 4301, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4301 = anonymous_6543
10933 { 4302, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4302 = anonymous_6545
11129 { 4498, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4498 = anonymous_6980
11130 { 4499, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4499 = anonymous_6982
11132 { 4501, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4501 = anonymous_6986
11133 { 4502, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4502 = anonymous_6988
11146 { 4515, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4515 = anonymous_7014
11147 { 4516, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4516 = anonymous_7016
11148 { 4517, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #4517 = anonymous_7018
11989 { 5358, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5358 = anonymous_8961
11990 { 5359, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5359 = anonymous_8963
11992 { 5361, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5361 = anonymous_8967
11993 { 5362, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5362 = anonymous_8969
12006 { 5375, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5375 = anonymous_8995
12007 { 5376, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5376 = anonymous_8997
12008 { 5377, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5377 = anonymous_8999
12204 { 5573, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5573 = anonymous_9434
12205 { 5574, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5574 = anonymous_9436
12207 { 5576, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5576 = anonymous_9440
12208 { 5577, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5577 = anonymous_9442
12221 { 5590, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5590 = anonymous_9468
12222 { 5591, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5591 = anonymous_9470
12223 { 5592, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5592 = anonymous_9472
12419 { 5788, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5788 = anonymous_9907
12420 { 5789, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5789 = anonymous_9909
12422 { 5791, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5791 = anonymous_9913
12423 { 5792, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5792 = anonymous_9915
12436 { 5805, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5805 = anonymous_9941
12437 { 5806, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5806 = anonymous_9943
12438 { 5807, 5, 1, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo720, -1 ,nullptr }, // Inst #5807 = anonymous_9945