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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6862 { 231, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #231 = CLZr64
7176 { 545, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #545 = GET_HI_INT64
7177 { 546, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #546 = GET_LO_INT64
7788 { 1157, 2, 1, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1157 = INT_PTX_LDG_GLOBAL_i32areg64
7803 { 1172, 2, 1, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1172 = INT_PTX_LDG_GLOBAL_p32areg64
7908 { 1277, 2, 1, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1277 = INT_PTX_LDU_GLOBAL_i32areg64
7923 { 1292, 2, 1, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1292 = INT_PTX_LDU_GLOBAL_p32areg64
8307 { 1676, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1676 = POPCr64
8819 { 2188, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2188 = SUQ_ARRAY_SIZE
8820 { 2189, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2189 = SUQ_CHANNEL_DATA_TYPE
8821 { 2190, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2190 = SUQ_CHANNEL_ORDER
8822 { 2191, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2191 = SUQ_DEPTH
8823 { 2192, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2192 = SUQ_HEIGHT
8824 { 2193, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2193 = SUQ_WIDTH
9249 { 2618, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2618 = TXQ_ARRAY_SIZE
9250 { 2619, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2619 = TXQ_CHANNEL_DATA_TYPE
9251 { 2620, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2620 = TXQ_CHANNEL_ORDER
9252 { 2621, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2621 = TXQ_DEPTH
9253 { 2622, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2622 = TXQ_HEIGHT
9254 { 2623, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2623 = TXQ_NUM_MIPMAP_LEVELS
9255 { 2624, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2624 = TXQ_NUM_SAMPLES
9256 { 2625, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2625 = TXQ_WIDTH
12470 { 5839, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #5839 = cvta_to_const_yes_3264
12473 { 5842, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #5842 = cvta_to_global_yes_3264
12476 { 5845, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #5845 = cvta_to_local_yes_3264
12479 { 5848, 2, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #5848 = cvta_to_shared_yes_3264