|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 9874 { 3243, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3243 = anonymous_4060
9875 { 3244, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3244 = anonymous_4065
9877 { 3246, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3246 = anonymous_4084
9878 { 3247, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3247 = anonymous_4089
9903 { 3272, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3272 = anonymous_4223
9904 { 3273, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3273 = anonymous_4228
10088 { 3457, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3457 = anonymous_4641
10089 { 3458, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3458 = anonymous_4644
10091 { 3460, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3460 = anonymous_4650
10092 { 3461, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3461 = anonymous_4653
10117 { 3486, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3486 = anonymous_4728
10118 { 3487, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3487 = anonymous_4731
10303 { 3672, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3672 = anonymous_5114
10304 { 3673, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3673 = anonymous_5117
10306 { 3675, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3675 = anonymous_5123
10307 { 3676, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3676 = anonymous_5126
10332 { 3701, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3701 = anonymous_5201
10333 { 3702, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #3702 = anonymous_5204
11163 { 4532, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4532 = anonymous_7051
11164 { 4533, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4533 = anonymous_7055
11166 { 4535, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4535 = anonymous_7063
11167 { 4536, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4536 = anonymous_7067
11192 { 4561, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4561 = anonymous_7170
11193 { 4562, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4562 = anonymous_7174
11378 { 4747, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4747 = anonymous_7568
11379 { 4748, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4748 = anonymous_7571
11381 { 4750, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4750 = anonymous_7577
11382 { 4751, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4751 = anonymous_7580
11407 { 4776, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4776 = anonymous_7655
11408 { 4777, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4777 = anonymous_7658
11593 { 4962, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4962 = anonymous_8041
11594 { 4963, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4963 = anonymous_8044
11596 { 4965, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4965 = anonymous_8050
11597 { 4966, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4966 = anonymous_8053
11622 { 4991, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4991 = anonymous_8128
11623 { 4992, 4, 2, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo630, -1 ,nullptr }, // Inst #4992 = anonymous_8131