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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 7063 { 432, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #432 = FADD_rnf64rr
7073 { 442, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #442 = FADDf64rr
7094 { 463, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #463 = FDIV64rr
7116 { 485, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #485 = FMAXf64rr
7122 { 491, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #491 = FMINf64rr
7137 { 506, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #506 = FMUL_rnf64rr
7147 { 516, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #516 = FMULf64rr
7163 { 532, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #532 = FSUB_rnf64rr
7173 { 542, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #542 = FSUBf64rr
7219 { 588, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #588 = INT_NVVM_ADD_RM_D
7222 { 591, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #591 = INT_NVVM_ADD_RN_D
7225 { 594, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #594 = INT_NVVM_ADD_RP_D
7228 { 597, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #597 = INT_NVVM_ADD_RZ_D
7245 { 614, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #614 = INT_NVVM_DIV_RM_D
7248 { 617, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #617 = INT_NVVM_DIV_RN_D
7251 { 620, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #620 = INT_NVVM_DIV_RP_D
7254 { 623, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #623 = INT_NVVM_DIV_RZ_D
7263 { 632, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #632 = INT_NVVM_FMAX_D
7278 { 647, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #647 = INT_NVVM_FMIN_D
7291 { 660, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #660 = INT_NVVM_MUL_RM_D
7294 { 663, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #663 = INT_NVVM_MUL_RN_D
7297 { 666, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #666 = INT_NVVM_MUL_RP_D
7300 { 669, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #669 = INT_NVVM_MUL_RZ_D