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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 7060 { 429, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #429 = FADD_rnf32rr
7061 { 430, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #430 = FADD_rnf32rr_ftz
7070 { 439, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #439 = FADDf32rr
7071 { 440, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #440 = FADDf32rr_ftz
7082 { 451, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #451 = FDIV32approxrr
7083 { 452, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #452 = FDIV32approxrr_ftz
7088 { 457, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #457 = FDIV32rr
7089 { 458, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #458 = FDIV32rr_ftz
7090 { 459, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #459 = FDIV32rr_prec
7091 { 460, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #460 = FDIV32rr_prec_ftz
7113 { 482, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #482 = FMAXf32rr
7114 { 483, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #483 = FMAXf32rr_ftz
7119 { 488, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #488 = FMINf32rr
7120 { 489, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #489 = FMINf32rr_ftz
7134 { 503, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #503 = FMUL_rnf32rr
7135 { 504, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #504 = FMUL_rnf32rr_ftz
7144 { 513, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #513 = FMULf32rr
7145 { 514, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #514 = FMULf32rr_ftz
7160 { 529, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #529 = FSUB_rnf32rr
7161 { 530, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #530 = FSUB_rnf32rr_ftz
7170 { 539, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #539 = FSUBf32rr
7171 { 540, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #540 = FSUBf32rr_ftz
7220 { 589, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #589 = INT_NVVM_ADD_RM_F
7221 { 590, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #590 = INT_NVVM_ADD_RM_FTZ_F
7223 { 592, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #592 = INT_NVVM_ADD_RN_F
7224 { 593, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #593 = INT_NVVM_ADD_RN_FTZ_F
7226 { 595, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #595 = INT_NVVM_ADD_RP_F
7227 { 596, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #596 = INT_NVVM_ADD_RP_FTZ_F
7229 { 598, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #598 = INT_NVVM_ADD_RZ_F
7230 { 599, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #599 = INT_NVVM_ADD_RZ_FTZ_F
7243 { 612, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #612 = INT_NVVM_DIV_APPROX_F
7244 { 613, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #613 = INT_NVVM_DIV_APPROX_FTZ_F
7246 { 615, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #615 = INT_NVVM_DIV_RM_F
7247 { 616, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #616 = INT_NVVM_DIV_RM_FTZ_F
7249 { 618, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #618 = INT_NVVM_DIV_RN_F
7250 { 619, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #619 = INT_NVVM_DIV_RN_FTZ_F
7252 { 621, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #621 = INT_NVVM_DIV_RP_F
7253 { 622, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #622 = INT_NVVM_DIV_RP_FTZ_F
7255 { 624, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #624 = INT_NVVM_DIV_RZ_F
7256 { 625, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #625 = INT_NVVM_DIV_RZ_FTZ_F
7264 { 633, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #633 = INT_NVVM_FMAX_F
7265 { 634, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #634 = INT_NVVM_FMAX_FTZ_F
7279 { 648, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #648 = INT_NVVM_FMIN_F
7280 { 649, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #649 = INT_NVVM_FMIN_FTZ_F
7292 { 661, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #661 = INT_NVVM_MUL_RM_F
7293 { 662, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #662 = INT_NVVM_MUL_RM_FTZ_F
7295 { 664, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #664 = INT_NVVM_MUL_RN_F
7296 { 665, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #665 = INT_NVVM_MUL_RN_FTZ_F
7298 { 667, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #667 = INT_NVVM_MUL_RP_F
7299 { 668, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #668 = INT_NVVM_MUL_RP_FTZ_F
7301 { 670, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #670 = INT_NVVM_MUL_RZ_F
7302 { 671, 3, 1, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #671 = INT_NVVM_MUL_RZ_FTZ_F