|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 1394 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
4189 case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
gen/lib/Target/Mips/MipsGenAsmWriter.inc 7507 MI->getOperand(2).getReg() == Mips::ZERO) {
7565 MI->getOperand(1).getReg() == Mips::ZERO) {
7573 MI->getOperand(0).getReg() == Mips::ZERO) {
7581 MI->getOperand(0).getReg() == Mips::ZERO) {
7591 MI->getOperand(1).getReg() == Mips::ZERO) {
8799 MI->getOperand(0).getReg() == Mips::ZERO) {
8833 MI->getOperand(0).getReg() == Mips::ZERO) {
8841 MI->getOperand(0).getReg() == Mips::ZERO) {
8849 MI->getOperand(0).getReg() == Mips::ZERO) {
8901 MI->getOperand(0).getReg() == Mips::ZERO) {
8909 MI->getOperand(0).getReg() == Mips::ZERO) {
8917 MI->getOperand(0).getReg() == Mips::ZERO) {
8925 MI->getOperand(0).getReg() == Mips::ZERO) {
8933 MI->getOperand(0).getReg() == Mips::ZERO) {
8941 MI->getOperand(0).getReg() == Mips::ZERO) {
8967 MI->getOperand(0).getReg() == Mips::ZERO &&
9114 MI->getOperand(0).getReg() == Mips::ZERO &&
9115 MI->getOperand(1).getReg() == Mips::ZERO) {
9166 MI->getOperand(0).getReg() == Mips::ZERO &&
9201 MI->getOperand(2).getReg() == Mips::ZERO) {
9318 MI->getOperand(0).getReg() == Mips::ZERO &&
9319 MI->getOperand(1).getReg() == Mips::ZERO &&
9329 MI->getOperand(0).getReg() == Mips::ZERO &&
9330 MI->getOperand(1).getReg() == Mips::ZERO &&
9340 MI->getOperand(0).getReg() == Mips::ZERO &&
9341 MI->getOperand(1).getReg() == Mips::ZERO &&
9375 MI->getOperand(1).getReg() == Mips::ZERO &&
9385 MI->getOperand(1).getReg() == Mips::ZERO &&
9397 MI->getOperand(1).getReg() == Mips::ZERO &&
9407 MI->getOperand(1).getReg() == Mips::ZERO &&
9419 MI->getOperand(1).getReg() == Mips::ZERO &&
9429 MI->getOperand(1).getReg() == Mips::ZERO &&
9441 MI->getOperand(1).getReg() == Mips::ZERO &&
9451 MI->getOperand(1).getReg() == Mips::ZERO &&
9463 MI->getOperand(1).getReg() == Mips::ZERO &&
9473 MI->getOperand(1).getReg() == Mips::ZERO &&
9485 MI->getOperand(1).getReg() == Mips::ZERO &&
9495 MI->getOperand(1).getReg() == Mips::ZERO &&
9746 MI->getOperand(0).getReg() == Mips::ZERO &&
gen/lib/Target/Mips/MipsGenDAGISel.inc 182 /* 221*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
1769 /* 3153*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
1784 /* 3179*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
1871 /* 3315*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
1885 /* 3339*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
1986 /* 3517*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2003 /* 3551*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2026 /* 3596*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2044 /* 3633*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2066 /* 3675*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2083 /* 3709*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2106 /* 3754*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2124 /* 3791*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2342 /* 4171*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2359 /* 4205*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2376 /* 4239*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2393 /* 4273*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2410 /* 4307*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2427 /* 4341*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2444 /* 4375*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2461 /* 4409*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2753 /* 4921*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2770 /* 4955*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2793 /* 5000*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2811 /* 5037*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2858 /* 5119*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2875 /* 5153*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2892 /* 5187*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2909 /* 5221*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2929 /* 5253*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
2944 /* 5279*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
10899 /* 20397*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
10924 /* 20441*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
10938 /* 20466*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
16500 /* 30598*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
16516 /* 30630*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
16725 /* 31078*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
16791 /* 31234*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17298 /* 32305*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17308 /* 32329*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17318 /* 32353*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17328 /* 32377*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17338 /* 32401*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17348 /* 32425*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17358 /* 32449*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17368 /* 32473*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17551 /* 32818*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17561 /* 32842*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17571 /* 32866*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17581 /* 32890*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17591 /* 32914*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17601 /* 32938*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17611 /* 32962*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
17621 /* 32986*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22787 /* 42683*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22794 /* 42697*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22822 /* 42755*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22835 /* 42779*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22863 /* 42837*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22870 /* 42851*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22898 /* 42909*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22905 /* 42923*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22933 /* 42981*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22940 /* 42995*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22968 /* 43053*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
22975 /* 43067*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23440 /* 43963*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23450 /* 43983*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23519 /* 44118*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23529 /* 44138*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23539 /* 44158*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
23591 /* 44279*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27283 /* 51633*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27290 /* 51646*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27297 /* 51659*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27316 /* 51696*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27325 /* 51716*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
27334 /* 51736*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29465 /* 55783*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29472 /* 55817*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29482 /* 55842*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29489 /* 55876*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29499 /* 55901*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29506 /* 55935*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29516 /* 55960*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29517 /* 55963*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29533 /* 56019*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29534 /* 56022*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29550 /* 56078*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
29551 /* 56081*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29571 /* 56145*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29578 /* 56179*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29588 /* 56204*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29595 /* 56238*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29605 /* 56263*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29612 /* 56297*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29622 /* 56322*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29623 /* 56325*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29639 /* 56381*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29640 /* 56384*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
29656 /* 56440*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29657 /* 56443*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
gen/lib/Target/Mips/MipsGenGlobalISel.inc 2592 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2635 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
2664 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
13620 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
13748 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
13908 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
14483 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15129 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15149 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15169 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15196 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15216 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15236 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15267 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15287 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15307 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15334 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15354 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
15374 GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0,
gen/lib/Target/Mips/MipsGenMCPseudoLowering.inc 67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
200 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
202 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
304 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
306 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
575 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
916 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 1615 { Mips::ZERO },
1967 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1997 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2077 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2087 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2137 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2247 Mips::ZERO,
2905 { Mips::ZERO, 0U },
3109 { Mips::ZERO, 0U },
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1969 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
1995 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
1997 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
2011 BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2012 BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2833 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
3146 case Mips::ZERO: return Mips::AT;
3177 case Mips::RA: return Mips::ZERO;
3308 unsigned TmpReg = Mips::ZERO;
3316 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
3425 unsigned TmpReg = Mips::ZERO;
3435 if (TmpReg != Mips::ZERO &&
3443 if (TmpReg != Mips::ZERO &&
3449 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3453 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3497 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3498 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3514 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3515 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3569 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3571 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3571 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3573 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3589 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3589 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3661 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
3704 if (BaseReg != Mips::ZERO)
3879 bool IsTrgRegZero = (TrgReg == Mips::ZERO);
3880 bool IsSrcRegZero = (SrcReg == Mips::ZERO);
3886 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3891 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3897 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3903 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3908 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
3908 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
3915 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3915 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3940 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3940 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3959 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
4002 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
4051 ZeroReg = Mips::ZERO;
4085 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4105 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
4116 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
4378 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4647 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4678 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4772 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4803 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4917 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
4920 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
5008 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
5015 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
5144 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5144 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5150 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
5175 if (SrcReg == Mips::ZERO) {
5218 return Mips::ZERO;
5268 case Mips::F0: return Mips::ZERO;
5307 case Mips::COP00: return Mips::ZERO;
5435 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5489 if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5505 if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5508 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 90 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
94 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp 225 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
225 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
227 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
234 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
240 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
257 return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
263 return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 1119 case Mips::ZERO: return 0;
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 63 return MI.getOperand(0).getReg() == Mips::ZERO;
93 if (MI.getOperand(0).getReg() == Mips::ZERO)
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 283 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
283 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
285 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
285 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
290 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
290 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
292 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
292 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
329 if (BaseReg != Mips::ZERO)
358 if (BaseReg != Mips::ZERO)
395 if (BaseReg != Mips::ZERO)
1245 emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1300 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
lib/Target/Mips/MicroMipsSizeReduction.cpp 575 if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 ||
lib/Target/Mips/MipsAsmPrinter.cpp 144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
1092 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1210 .addReg(Mips::ZERO)
1211 .addReg(Mips::ZERO)
1216 .addReg(Mips::ZERO)
1217 .addReg(Mips::ZERO)
lib/Target/Mips/MipsDelaySlotFiller.cpp 380 CallerSavedRegs.reset(Mips::ZERO);
398 AllocSet.set(Mips::ZERO);
lib/Target/Mips/MipsExpandPseudo.cpp 84 unsigned ZERO = Mips::ZERO;
232 ZERO = Mips::ZERO;
413 .addReg(Mips::ZERO)
445 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
508 ZERO = Mips::ZERO;
lib/Target/Mips/MipsFastISel.cpp 370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
lib/Target/Mips/MipsISelLowering.cpp 1277 .addReg(Mips::ZERO)
1685 .addReg(Mips::ZERO).addImm(MaskImm);
1688 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1866 .addReg(Mips::ZERO).addImm(MaskImm);
1869 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2323 DAG.getRegister(Mips::ZERO, MVT::i32),
4464 .addReg(Mips::ZERO)
4534 .addReg(Mips::ZERO)
lib/Target/Mips/MipsInstrInfo.cpp 467 (I->getOperand(0).getReg() == Mips::ZERO ||
470 (I->getOperand(1).getReg() == Mips::ZERO ||
611 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
lib/Target/Mips/MipsInstructionSelector.cpp 134 MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
146 MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
307 .addUse(Mips::ZERO)
655 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
759 .addUse(Mips::ZERO)
775 .addUse(Mips::ZERO)
lib/Target/Mips/MipsRegisterInfo.cpp 152 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
lib/Target/Mips/MipsSEFrameLowering.cpp 636 unsigned SrcReg = Mips::ZERO;
666 .addReg(Mips::ZERO)
675 .addReg(Mips::ZERO)
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 88 (MI.getOperand(1).getReg() == Mips::ZERO) &&
92 ZeroReg = Mips::ZERO;
143 .addUse(Mips::ZERO);
253 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
777 Mips::ZERO, MVT::i32);
782 Mips::ZERO, MVT::i32);
1041 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1064 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1086 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1142 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
lib/Target/Mips/MipsSEISelLowering.cpp 3069 .addReg(Mips::ZERO).addImm(0);
3075 .addReg(Mips::ZERO).addImm(1);
3138 .addReg(Mips::ZERO).addImm(0);
3144 .addReg(Mips::ZERO).addImm(1);
3421 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
lib/Target/Mips/MipsSEInstrInfo.cpp 95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
617 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
885 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
tools/llvm-exegesis/lib/Mips/Target.cpp 42 .addReg(Mips::ZERO)
unittests/tools/llvm-exegesis/Mips/TargetTest.cpp 49 ElementsAre(IsReg(Reg), IsReg(Mips::ZERO), IsImm(Value)));