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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3957 { 16, 16, 128, VTLists+4 }, // MSA128F16
3958 { 32, 32, 32, VTLists+0 }, // CCR
3959 { 32, 32, 32, VTLists+0 }, // COP0
3960 { 32, 32, 32, VTLists+0 }, // COP2
3961 { 32, 32, 32, VTLists+0 }, // COP3
3962 { 32, 32, 32, VTLists+12 }, // DSPR
3963 { 32, 32, 32, VTLists+6 }, // FGR32
3964 { 32, 32, 32, VTLists+0 }, // FGRCC
3965 { 32, 32, 32, VTLists+0 }, // GPR32
3966 { 32, 32, 32, VTLists+0 }, // HWRegs
3967 { 32, 32, 32, VTLists+0 }, // MSACtrl
3968 { 32, 32, 32, VTLists+0 }, // GPR32NONZERO
3969 { 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP
3970 { 32, 32, 32, VTLists+0 }, // CPU16Regs
3971 { 32, 32, 32, VTLists+0 }, // FCC
3972 { 32, 32, 32, VTLists+0 }, // GPRMM16
3973 { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP
3974 { 32, 32, 32, VTLists+0 }, // GPRMM16Zero
3975 { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero
3976 { 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP
3977 { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond
3978 { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP
3979 { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero
3980 { 32, 32, 32, VTLists+0 }, // HI32DSP
3981 { 32, 32, 32, VTLists+0 }, // LO32DSP
3982 { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond
3983 { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst
3984 { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3985 { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3986 { 32, 32, 32, VTLists+0 }, // CPURAReg
3987 { 32, 32, 32, VTLists+0 }, // CPUSPReg
3988 { 32, 32, 32, VTLists+12 }, // DSPCC
3989 { 32, 32, 32, VTLists+0 }, // GP32
3990 { 32, 32, 32, VTLists+0 }, // GPR32ZERO
3991 { 32, 32, 32, VTLists+0 }, // HI32
3992 { 32, 32, 32, VTLists+0 }, // LO32
3993 { 32, 32, 32, VTLists+0 }, // SP32
3994 { 64, 64, 64, VTLists+8 }, // FGR64
3995 { 64, 64, 64, VTLists+2 }, // GPR64
3996 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO
3997 { 64, 64, 64, VTLists+8 }, // AFGR64
3998 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
3999 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs
4000 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP
4001 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero
4002 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4003 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4004 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4005 { 64, 64, 64, VTLists+24 }, // ACC64DSP
4006 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4007 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4008 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4009 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4010 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4011 { 64, 64, 64, VTLists+2 }, // OCTEON_MPL
4012 { 64, 64, 64, VTLists+2 }, // OCTEON_P
4013 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4014 { 64, 64, 64, VTLists+24 }, // ACC64
4015 { 64, 64, 64, VTLists+2 }, // GP64
4016 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg
4017 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO
4018 { 64, 64, 64, VTLists+2 }, // HI64
4019 { 64, 64, 64, VTLists+2 }, // LO64
4020 { 64, 64, 64, VTLists+2 }, // SP64
4021 { 128, 128, 128, VTLists+10 }, // MSA128B
4022 { 128, 128, 128, VTLists+21 }, // MSA128D
4023 { 128, 128, 128, VTLists+15 }, // MSA128H
4024 { 128, 128, 128, VTLists+18 }, // MSA128W
4025 { 128, 128, 128, VTLists+18 }, // MSA128WEvens
4026 { 128, 128, 128, VTLists+24 }, // ACC128