|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 4218 case Mips::SP: OpKind = MCK_CPUSPReg; break;
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4429 static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 1614 { Mips::SP },
1967 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1997 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2027 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2037 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2217 Mips::SP,
2277 Mips::SP,
2904 { Mips::SP, 29U },
3108 { Mips::SP, 29U },
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1335 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1341 && (getMemBase()->getGPR32Reg() == Mips::SP);
3174 case Mips::GP: return Mips::SP;
3175 case Mips::SP: return Mips::FP;
3728 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
5297 case Mips::F29: return Mips::SP;
5336 case Mips::COP029: return Mips::SP;
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 1806 Inst.addOperand(MCOperand::createReg(Mips::SP));
1847 Inst.addOperand(MCOperand::createReg(Mips::SP));
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 74 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 828 (MI.getOperand(OpNo).getReg() == Mips::SP ||
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 88 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 70 && MI.getOperand(0).getReg() == Mips::SP);
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
259 return Reg != Mips::SP && Reg != Mips::T8;
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 298 emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
1224 emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1248 emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1304 Inst.addOperand(MCOperand::createReg(Mips::SP));
lib/Target/Mips/MicroMipsSizeReduction.cpp 287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
384 Mips::SP, Mips::FP, Mips::RA};
lib/Target/Mips/Mips16FrameLowering.cpp 62 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
88 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
109 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
lib/Target/Mips/Mips16InstrInfo.cpp 294 MIB2.addReg(Mips::SP, RegState::Kill);
299 Mips::SP);
406 if (FrameReg == Mips::SP) {
420 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
490 if ((Reg == Mips::PC) || (Reg == Mips::SP))
lib/Target/Mips/Mips16RegisterInfo.cpp 102 FrameReg = Mips::SP;
112 FrameReg = Mips::SP;
lib/Target/Mips/MipsBranchExpansion.cpp 456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
457 .addReg(Mips::SP)
461 .addReg(Mips::SP)
506 .addReg(Mips::SP)
517 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
518 .addReg(Mips::SP)
525 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
526 .addReg(Mips::SP)
lib/Target/Mips/MipsCallLowering.cpp 295 MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
571 MIB.addDef(Mips::SP, RegState::Implicit);
lib/Target/Mips/MipsDelaySlotFiller.cpp 711 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
lib/Target/Mips/MipsFastISel.cpp 1263 Addr.setReg(Mips::SP);
lib/Target/Mips/MipsFrameLowering.cpp 140 unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
lib/Target/Mips/MipsISelLowering.cpp 524 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
3117 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
lib/Target/Mips/MipsRegisterInfo.cpp 152 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
288 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
291 (IsN64 ? Mips::SP_64 : Mips::SP);
lib/Target/Mips/MipsSEFrameLowering.cpp 306 && I->getOperand(3).getReg() == Mips::SP) {
371 && I->getOperand(3).getReg() == Mips::SP) {
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 146 .addDef(Mips::SP)
147 .addUse(Mips::SP)
171 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
178 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
lib/Target/Mips/MipsSEInstrInfo.cpp 882 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;