reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc
 3894   extern const TargetRegisterClass MSA128DRegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc
  228     return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  296     return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  358     return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  388     return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  416     return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  587     return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  615     return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  643     return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  701     return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  780     return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
  810     return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
 1303     return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1431     return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1493     return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1553     return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1613     return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1673     return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1763     return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1903     return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1995     return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2060     return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2109     return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2157     return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2220     return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2290     return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2355     return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2449     return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2556     return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2606     return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2654     return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2723     return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2800     return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2991     return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3039     return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3087     return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3135     return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3291     return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3339     return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3387     return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenRegisterInfo.inc
 4720   &Mips::MSA128DRegClass,
 4737   &Mips::MSA128DRegClass,
 4745   &Mips::MSA128DRegClass,
 4753   &Mips::MSA128DRegClass,
 5704     &Mips::MSA128DRegClass,
lib/Target/Mips/MipsISelLowering.cpp
 3980         return std::make_pair(0U, &Mips::MSA128DRegClass);
lib/Target/Mips/MipsSEISelLowering.cpp
  120     addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
  123     addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
 3227     Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
 3289   Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
 3370     VecRC = &Mips::MSA128DRegClass;
 3482   Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
 3483   Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
 3784     WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
 3850   const TargetRegisterClass *RC = &Mips::MSA128DRegClass;