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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3867 extern const TargetRegisterClass GPR64RegClass;
References
gen/lib/Target/Mips/MipsGenFastISel.inc 98 return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
146 return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
149 return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
152 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
155 return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
189 return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
192 return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
260 return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
722 return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
847 return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
850 return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
883 return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
923 return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
994 return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
997 return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
1000 return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1003 return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1249 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1340 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1395 return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1715 return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1718 return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1799 return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1830 return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1867 return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1959 return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2254 return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2395 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2489 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2520 return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2687 return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2764 return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2947 return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3717 return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3735 return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3753 return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3771 return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 4572 &Mips::GPR64RegClass,
4577 &Mips::GPR64RegClass,
4583 &Mips::GPR64RegClass,
4590 &Mips::GPR64RegClass,
4595 &Mips::GPR64RegClass,
4600 &Mips::GPR64RegClass,
4609 &Mips::GPR64RegClass,
4616 &Mips::GPR64RegClass,
4622 &Mips::GPR64RegClass,
4632 &Mips::GPR64RegClass,
4639 &Mips::GPR64RegClass,
4650 &Mips::GPR64RegClass,
4660 &Mips::GPR64RegClass,
4674 &Mips::GPR64RegClass,
4692 &Mips::GPR64RegClass,
4698 &Mips::GPR64RegClass,
4704 &Mips::GPR64RegClass,
4712 &Mips::GPR64RegClass,
5677 &Mips::GPR64RegClass,
lib/Target/Mips/MipsISelLowering.cpp 3969 return std::make_pair(0U, &Mips::GPR64RegClass);
3993 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
lib/Target/Mips/MipsMachineFunction.cpp 42 return Mips::GPR64RegClass;
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
155 ? Mips::GPR64RegClass
lib/Target/Mips/MipsRegisterInfo.cpp 54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSEFrameLowering.cpp 422 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
896 Mips::GPR64RegClass : Mips::GPR32RegClass;
913 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
lib/Target/Mips/MipsSEISelLowering.cpp 70 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
3339 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3525 : &Mips::GPR64RegClass);
3531 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3577 : &Mips::GPR64RegClass);
3669 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3773 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSEInstrInfo.cpp 149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150 if (Mips::GPR64RegClass.contains(SrcReg))
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
261 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
339 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
619 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSERegisterInfo.cpp 59 return &Mips::GPR64RegClass;
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSubtarget.cpp 228 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
tools/llvm-exegesis/lib/Mips/Target.cpp 51 if (Mips::GPR64RegClass.contains(Reg))