|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3837 extern const TargetRegisterClass GPR32RegClass;
References
gen/lib/Target/Mips/MipsGenFastISel.inc 83 return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
86 return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
89 return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
122 return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
125 return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
128 return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
131 return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
134 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
137 return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
174 return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
177 return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
180 return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
251 return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
829 return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
835 return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
838 return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
867 return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
870 return fastEmitInst_r(Mips::PseudoMFHI_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
873 return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
876 return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
907 return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
910 return fastEmitInst_r(Mips::PseudoMFLO_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
913 return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
916 return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
970 return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
973 return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
976 return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
979 return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
982 return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
985 return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
1093 return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1099 return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1105 return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1111 return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1129 return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1135 return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1141 return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1147 return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1165 return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1180 return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1237 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1240 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1328 return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1331 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1359 return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1380 return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1383 return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1386 return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1697 return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1700 return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1703 return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1706 return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1787 return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1790 return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1818 return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1821 return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1852 return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1855 return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1858 return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1926 return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1929 return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1947 return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1950 return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2018 return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2024 return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2178 return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2184 return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2242 return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2245 return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2313 return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2319 return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2383 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2386 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2474 return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2477 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2480 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2508 return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2511 return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2675 return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2678 return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2749 return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2752 return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2755 return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2941 return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3459 return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3462 return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3612 return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3615 return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3633 return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3639 return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3657 return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3663 return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3681 return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3687 return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3855 return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3909 return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 4379 &Mips::GPR32RegClass,
4385 &Mips::GPR32RegClass,
4392 &Mips::GPR32RegClass,
4400 &Mips::GPR32RegClass,
4409 &Mips::GPR32RegClass,
4415 &Mips::GPR32RegClass,
4421 &Mips::GPR32RegClass,
4432 &Mips::GPR32RegClass,
4440 &Mips::GPR32RegClass,
4447 &Mips::GPR32RegClass,
4459 &Mips::GPR32RegClass,
4467 &Mips::GPR32RegClass,
4480 &Mips::GPR32RegClass,
4492 &Mips::GPR32RegClass,
4508 &Mips::GPR32RegClass,
4523 &Mips::GPR32RegClass,
4530 &Mips::GPR32RegClass,
4538 &Mips::GPR32RegClass,
4545 &Mips::GPR32RegClass,
4564 &Mips::GPR32RegClass,
5647 &Mips::GPR32RegClass,
lib/Target/Mips/Mips16InstrInfo.cpp 76 Mips::GPR32RegClass.contains(SrcReg))
78 else if (Mips::GPR32RegClass.contains(DestReg) &&
lib/Target/Mips/MipsAsmPrinter.cpp 334 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
353 } else if (Mips::GPR32RegClass.contains(Reg))
lib/Target/Mips/MipsFastISel.cpp 329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
396 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
402 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
404 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
415 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
437 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
653 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
659 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
671 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
677 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
689 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
695 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
741 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
742 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
765 ResultReg = createResultReg(&Mips::GPR32RegClass);
769 ResultReg = createResultReg(&Mips::GPR32RegClass);
773 ResultReg = createResultReg(&Mips::GPR32RegClass);
962 ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
988 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1035 RC = &Mips::GPR32RegClass;
1054 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1127 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1392 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1412 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1603 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1614 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1627 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1635 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1824 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1845 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1913 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1949 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1968 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1980 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2106 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2117 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2118 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
lib/Target/Mips/MipsISelLowering.cpp 3964 return std::make_pair(0U, &Mips::GPR32RegClass);
3967 return std::make_pair(0U, &Mips::GPR32RegClass);
3991 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
lib/Target/Mips/MipsInstructionSelector.cpp 96 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
117 return &Mips::GPR32RegClass;
151 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
317 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
325 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
333 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
345 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
483 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
494 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
495 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
574 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
587 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
642 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
756 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
792 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
lib/Target/Mips/MipsMachineFunction.cpp 44 return Mips::GPR32RegClass;
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
156 : Mips::GPR32RegClass;
168 const TargetRegisterClass &RC = Mips::GPR32RegClass;
lib/Target/Mips/MipsRegisterInfo.cpp 54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSEFrameLowering.cpp 317 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
591 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
754 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
896 Mips::GPR64RegClass : Mips::GPR32RegClass;
913 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
lib/Target/Mips/MipsSEISelLowering.cpp 67 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
3038 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3107 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3339 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3524 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3526 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3527 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3576 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3579 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3588 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3669 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3773 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSEInstrInfo.cpp 90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
259 if (Mips::GPR32RegClass.hasSubClassEq(RC))
337 if (Mips::GPR32RegClass.hasSubClassEq(RC))
619 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSERegisterInfo.cpp 56 return &Mips::GPR32RegClass;
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
lib/Target/Mips/MipsSubtarget.cpp 229 : &Mips::GPR32RegClass);
tools/llvm-exegesis/lib/Mips/Target.cpp 49 if (Mips::GPR32RegClass.contains(Reg))