reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 3866   extern const TargetRegisterClass FGR64RegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc

   74     return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
  331     return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
  337     return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
  450     return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
  456     return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
  483     return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
  503     return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
  506     return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
  674     return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
  680     return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
  742     return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
  762     return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
  949     return fastEmitInst_r(Mips::MTC1_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
  952     return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
 1033     return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
 1067     return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
 1466     return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1472     return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1526     return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1532     return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1586     return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1592     return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1646     return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1652     return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2823     return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3828     return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 5676     &Mips::FGR64RegClass,

lib/Target/Mips/MipsISelLowering.cpp

 3985           return std::make_pair(0U, &Mips::FGR64RegClass);

lib/Target/Mips/MipsInstructionSelector.cpp

  101       RC = STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  122                : STI.hasMips32r6() || STI.isFP64bit() ? &Mips::FGR64RegClass

lib/Target/Mips/MipsRegisterInfo.cpp

  187     for (MCPhysReg Reg : Mips::FGR64RegClass)

lib/Target/Mips/MipsSEFrameLowering.cpp

  319         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  384         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  480       } else if (Mips::FGR64RegClass.contains(Reg)) {

lib/Target/Mips/MipsSEISelLowering.cpp

  176         addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
 3791                         ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)

lib/Target/Mips/MipsSEInstrInfo.cpp

  147   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
  156     else if (Mips::FGR64RegClass.contains(SrcReg))
  164     else if (Mips::FGR64RegClass.contains(DestReg))
  275   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
  353   else if (Mips::FGR64RegClass.hasSubClassEq(RC))