reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 3835   extern const TargetRegisterClass FGR32RegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc

   59     return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
   62     return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
   65     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
  319     return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
  322     return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
  435     return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
  438     return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
  441     return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
  476     return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
  542     return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
  545     return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
  548     return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
  551     return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
  662     return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
  665     return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
  737   return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1020     return fastEmitInst_r(Mips::TRUNC_W_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1023     return fastEmitInst_r(Mips::TRUNC_W_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1026     return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1048     return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1051     return fastEmitInst_r(Mips::CVT_W_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1054     return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1057     return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1060     return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
 1454     return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1457     return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1514     return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1517     return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1574     return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1577     return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1634     return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1637     return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3801     return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 4368   &Mips::FGR32RegClass,
 5645     &Mips::FGR32RegClass,

lib/Target/Mips/MipsAsmPrinter.cpp

  335   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
  346     if (Mips::FGR32RegClass.contains(Reg)) {

lib/Target/Mips/MipsFastISel.cpp

  394     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
  779     ResultReg = createResultReg(&Mips::FGR32RegClass);
 1038     RC = &Mips::FGR32RegClass;
 1089   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
 1128   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
 1429       Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);

lib/Target/Mips/MipsISelLowering.cpp

 3982         return std::make_pair(0U, &Mips::FGR32RegClass);

lib/Target/Mips/MipsInstructionSelector.cpp

   99       RC = &Mips::FGR32RegClass;
  121                ? &Mips::FGR32RegClass
  535     Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);

lib/Target/Mips/MipsSEISelLowering.cpp

  171     addRegisterClass(MVT::f32, &Mips::FGR32RegClass);

lib/Target/Mips/MipsSEInstrInfo.cpp

   98     else if (Mips::FGR32RegClass.contains(SrcReg))
  121     else if (Mips::FGR32RegClass.contains(DestReg))
  143   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
  271   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
  349   else if (Mips::FGR32RegClass.hasSubClassEq(RC))