reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 3842   extern const TargetRegisterClass CPU16RegsRegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc

  119     return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
  832     return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
 1234     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1377     return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1694     return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1849     return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2021     return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2181     return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2316     return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2380     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2746     return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2875     return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2924     return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3636     return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
 3660     return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
 3684     return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
 4012     return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 4403   &Mips::CPU16RegsRegClass,
 4424   &Mips::CPU16RegsRegClass,
 4450   &Mips::CPU16RegsRegClass,
 4470   &Mips::CPU16RegsRegClass,
 4483   &Mips::CPU16RegsRegClass,
 4495   &Mips::CPU16RegsRegClass,
 4511   &Mips::CPU16RegsRegClass,
 5652     &Mips::CPU16RegsRegClass,

lib/Target/Mips/Mips16ISelDAGToDAG.cpp

   76   const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;

lib/Target/Mips/Mips16ISelLowering.cpp

  125   addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);

lib/Target/Mips/Mips16InstrInfo.cpp

   75   if (Mips::CPU16RegsRegClass.contains(DestReg) &&
   79            Mips::CPU16RegsRegClass.contains(SrcReg))
   82            (Mips::CPU16RegsRegClass.contains(DestReg)))
   85            (Mips::CPU16RegsRegClass.contains(DestReg)))
  120   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  139   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  356       (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
  382   BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);

lib/Target/Mips/Mips16RegisterInfo.cpp

   72   return &Mips::CPU16RegsRegClass;

lib/Target/Mips/MipsISelLowering.cpp

 3963           return std::make_pair(0U, &Mips::CPU16RegsRegClass);

lib/Target/Mips/MipsMachineFunction.cpp

   36     return Mips::CPU16RegsRegClass;