|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmWriter.inc 7637 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7639 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7649 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7651 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7709 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7711 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7721 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7723 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7781 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7783 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7793 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7795 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7853 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7855 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7865 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7867 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7925 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7927 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7937 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7939 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
7997 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
7999 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8009 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8011 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8069 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8071 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8081 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8083 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8141 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8143 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8153 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8155 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8213 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8215 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8225 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8227 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8285 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8287 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8297 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8299 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8357 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8359 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8369 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8371 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8429 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8431 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8441 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8443 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8501 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8503 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8513 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8515 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8573 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8575 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8585 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8587 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8645 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8647 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8657 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8659 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8717 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8719 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
8729 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
8731 MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
gen/lib/Target/Mips/MipsGenGlobalISel.inc17905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
17914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
17915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
17933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
17942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
17943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
18707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
18716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
18717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
19772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19777 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
19778 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
19822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
19823 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
19862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
19882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
19883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
19884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20921 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20922 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20923 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20975 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
20976 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
20993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
20998 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21003 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21004 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21057 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21058 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21083 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21084 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21137 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21138 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21139 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
21155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
21579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
21580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
22381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
22382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4517 static const MCOperandInfo OperandInfo55[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4527 static const MCOperandInfo OperandInfo65[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4567 static const MCOperandInfo OperandInfo105[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4584 static const MCOperandInfo OperandInfo122[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4596 static const MCOperandInfo OperandInfo134[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4596 static const MCOperandInfo OperandInfo134[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4596 static const MCOperandInfo OperandInfo134[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4601 static const MCOperandInfo OperandInfo139[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4601 static const MCOperandInfo OperandInfo139[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4601 static const MCOperandInfo OperandInfo139[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4607 static const MCOperandInfo OperandInfo145[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4609 static const MCOperandInfo OperandInfo147[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4655 static const MCOperandInfo OperandInfo193[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4674 static const MCOperandInfo OperandInfo212[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4676 static const MCOperandInfo OperandInfo214[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4676 static const MCOperandInfo OperandInfo214[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4698 static const MCOperandInfo OperandInfo236[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4698 static const MCOperandInfo OperandInfo236[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4699 static const MCOperandInfo OperandInfo237[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4699 static const MCOperandInfo OperandInfo237[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4699 static const MCOperandInfo OperandInfo237[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4702 static const MCOperandInfo OperandInfo240[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4702 static const MCOperandInfo OperandInfo240[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4735 static const MCOperandInfo OperandInfo273[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4753 static const MCOperandInfo OperandInfo291[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4753 static const MCOperandInfo OperandInfo291[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4753 static const MCOperandInfo OperandInfo291[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4753 static const MCOperandInfo OperandInfo291[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4758 static const MCOperandInfo OperandInfo296[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4762 static const MCOperandInfo OperandInfo300[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4762 static const MCOperandInfo OperandInfo300[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4762 static const MCOperandInfo OperandInfo300[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4771 static const MCOperandInfo OperandInfo309[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4771 static const MCOperandInfo OperandInfo309[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4771 static const MCOperandInfo OperandInfo309[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4777 static const MCOperandInfo OperandInfo315[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4777 static const MCOperandInfo OperandInfo315[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/Mips/MipsGenRegisterBank.inc 43 (1u << (Mips::AFGR64RegClassID - 32)) |
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 2714 { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 1, true },
5276 &MipsMCRegisterClasses[AFGR64RegClassID],
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 897 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 2073 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
lib/Target/Mips/MipsOptionRecord.h 51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
lib/Target/Mips/MipsRegisterBankInfo.cpp 96 case Mips::AFGR64RegClassID:
lib/Target/Mips/MipsRegisterInfo.cpp 80 case Mips::AFGR64RegClassID: