reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 3869   extern const TargetRegisterClass AFGR64RegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc

  334     return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  340     return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  453     return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  459     return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  500     return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  509     return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  677     return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  683     return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
  745     return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
 1469     return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1475     return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1529     return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1535     return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1589     return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1595     return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1649     return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1655     return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2826     return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 5679     &Mips::AFGR64RegClass,

lib/Target/Mips/MipsAsmPrinter.cpp

  336   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
  349     } else if (Mips::AFGR64RegClass.contains(Reg)) {

lib/Target/Mips/MipsFastISel.cpp

  400     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
  785     ResultReg = createResultReg(&Mips::AFGR64RegClass);
 1012   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
 1041     RC = &Mips::AFGR64RegClass;
 1448       Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);

lib/Target/Mips/MipsISelLowering.cpp

 3932     if (RC == &Mips::AFGR64RegClass) {
 3986         return std::make_pair(0U, &Mips::AFGR64RegClass);

lib/Target/Mips/MipsInstructionSelector.cpp

  101       RC = STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  123                                                       : &Mips::AFGR64RegClass;

lib/Target/Mips/MipsRegisterInfo.cpp

  183     for (MCPhysReg Reg : Mips::AFGR64RegClass)

lib/Target/Mips/MipsSEFrameLowering.cpp

  319         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  384         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
  462       if (Mips::AFGR64RegClass.contains(Reg)) {

lib/Target/Mips/MipsSEISelLowering.cpp

  178         addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);

lib/Target/Mips/MipsSEInstrInfo.cpp

  145   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
  273   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
  351   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))