reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 3886   extern const TargetRegisterClass ACC64RegClass;

References

gen/lib/Target/Mips/MipsGenFastISel.inc

 2844     return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2847     return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2893     return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2896     return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3156     return fastEmitInst_rr(Mips::PseudoMTLOHI_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3162     return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3193     return fastEmitInst_rr(Mips::PseudoMULT_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3199     return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3230     return fastEmitInst_rr(Mips::PseudoMULTu_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3236     return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 5696     &Mips::ACC64RegClass,

lib/Target/Mips/MipsInstructionSelector.cpp

  266     Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
  424     Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);

lib/Target/Mips/MipsSEFrameLowering.cpp

   50   if (Mips::ACC64RegClass.contains(Src))

lib/Target/Mips/MipsSEISelLowering.cpp

  310     return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;

lib/Target/Mips/MipsSEInstrInfo.cpp

  263   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
  341   else if (Mips::ACC64RegClass.hasSubClassEq(RC))