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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 8047 { 9599 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8054 { 9599 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8061 { 9615 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8064 { 9615 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 3352 /* 6031*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3438 /* 6206*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3701 /* 6753*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3707 /* 6774*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3724 /* 6813*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3730 /* 6834*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3955 /* 7383*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3963 /* 7411*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3982 /* 7457*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
3990 /* 7485*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
10957 /* 20503*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16592 /* 30808*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16603 /* 30834*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16739 /* 31115*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16750 /* 31141*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16761 /* 31167*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
16772 /* 31193*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17005 /* 31718*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17016 /* 31744*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17082 /* 31884*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17093 /* 31910*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17104 /* 31936*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
17115 /* 31962*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
gen/lib/Target/Mips/MipsGenGlobalISel.inc13928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
13950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
14197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16742 { Mips::XORi, Mips::XORi, Mips::XORi_MM },
16742 { Mips::XORi, Mips::XORi, Mips::XORi_MM },
16821 { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },
16821 { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 6313 case Mips::XORi:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 2489 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64:
4207 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
4412 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4452 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4467 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4574 case Mips::XORi:
5187 Opc = Mips::XORi;
lib/Target/Mips/MipsFastISel.cpp 673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
lib/Target/Mips/MipsISelLowering.cpp 1680 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1861 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
lib/Target/Mips/MipsInstructionSelector.cpp 634 if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
662 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
669 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
676 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
683 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);