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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 8044 { 9599 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8051 { 9599 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 4781 /* 9139*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
4794 /* 9166*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
4859 /* 9301*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
4872 /* 9328*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
6019 /* 11656*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
6033 /* 11685*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
6103 /* 11830*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
6117 /* 11859*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
11009 /* 20602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_MM), 0,
16780 /* 31208*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
16792 /* 31237*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
gen/lib/Target/Mips/MipsGenFastISel.inc 2752 return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenGlobalISel.inc 2698 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
14453 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
14476 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17077 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17247 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17281 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17451 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
17485 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
19333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16741 { Mips::XOR, Mips::XOR, Mips::XOR_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 7912 case Mips::XOR_MM: {
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 4596 FinalOpcode = Mips::XOR_MM;
lib/Target/Mips/MicroMipsSizeReduction.cpp 278 {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,