reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc

 8043   { 9599 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
 8050   { 9599 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },

gen/lib/Target/Mips/MipsGenDAGISel.inc

 4629 /*  8819*/          OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 4694 /*  8954*/          OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 4707 /*  8982*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 4715 /*  9003*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5767 /* 11134*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5781 /* 11163*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5851 /* 11308*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5865 /* 11337*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5935 /* 11482*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
 5949 /* 11511*/            OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
10991 /* 20569*/            OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR), 0,
16714 /* 31052*/          OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
16726 /* 31081*/          OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,

gen/lib/Target/Mips/MipsGenFastISel.inc

 2755     return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Mips/MipsGenGlobalISel.inc

 2676         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
13879           GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
13901           GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
15995       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16029       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16403       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
16437       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18415       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18483       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18687       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
18721       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
19027       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,
19095       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR,

gen/lib/Target/Mips/MipsGenInstrInfo.inc

16741   { Mips::XOR, Mips::XOR, Mips::XOR_MM },
16741   { Mips::XOR, Mips::XOR, Mips::XOR_MM },
16820   { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },
16820   { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },

gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc

 5048     case Mips::XOR:

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 4575       FinalOpcode = Mips::XOR;
 5145     TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
 5199     TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);

lib/Target/Mips/MicroMipsSizeReduction.cpp

  276     {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,

lib/Target/Mips/MipsExpandPseudo.cpp

  371     Opcode = Mips::XOR;
  540     Opcode = Mips::XOR;

lib/Target/Mips/MipsFastISel.cpp

  311     Opc = Mips::XOR;
  654     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
  660     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);

lib/Target/Mips/MipsInstructionSelector.cpp

  650       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
  654       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);