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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7596 { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7600 { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7721 { 8461 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 2425 /* 4333*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
2459 /* 4401*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
2492 /* 4465*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
2524 /* 4525*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
4742 /* 9058*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
4768 /* 9112*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
4820 /* 9220*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
4846 /* 9274*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
5977 /* 11569*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
6005 /* 11627*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
6061 /* 11743*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
6089 /* 11801*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
16517 /* 30633*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
16690 /* 31007*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
16706 /* 31037*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
16794 /* 31245*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
16813 /* 31286*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
16835 /* 31338*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
gen/lib/Target/Mips/MipsGenGlobalISel.inc13746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
13862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
14481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
14522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
14561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM,
14602 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
16941 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17009 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17145 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17349 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
17417 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19197 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
19265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16694 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 7909 case Mips::SLTu_MM:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 4593 FinalOpcode = Mips::SLTu_MM;