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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7595 { 8069 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7599 { 8069 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7720 { 8461 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 2357 /* 4197*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
2391 /* 4265*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
4590 /* 8738*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
4616 /* 8792*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
4655 /* 8873*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
4681 /* 8927*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5725 /* 11047*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5753 /* 11105*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5809 /* 11221*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5837 /* 11279*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5893 /* 11395*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
5921 /* 11453*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
16501 /* 30601*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
16658 /* 30947*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
16674 /* 30977*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
16728 /* 31089*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
16747 /* 31130*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
16769 /* 31182*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
gen/lib/Target/Mips/MipsGenGlobalISel.inc13618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
13945 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
13982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu,
14021 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15893 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
15961 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
16301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
16369 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18177 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18245 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18585 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18653 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
18857 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16694 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
16694 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 5027 case Mips::SLTu:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 3996 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
4404 OpCode = Mips::SLTu;
4441 OpRegCode = Mips::SLTu;
4497 OpCode = Mips::SLTu;
4572 FinalOpcode = Mips::SLTu;
lib/Target/Mips/MipsFastISel.cpp 661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
lib/Target/Mips/MipsInstructionSelector.cpp 655 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
658 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
661 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
665 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
668 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);