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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7587 { 8065 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7591 { 8065 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7703 { 8446 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 2340 /* 4163*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
2374 /* 4231*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
4577 /* 8711*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
4603 /* 8765*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
4642 /* 8846*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
4668 /* 8900*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5711 /* 11018*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5739 /* 11076*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5795 /* 11192*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5823 /* 11250*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5879 /* 11366*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
5907 /* 11424*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
16650 /* 30932*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT), 0,
16666 /* 30962*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT), 0,
16736 /* 31104*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
16758 /* 31156*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
gen/lib/Target/Mips/MipsGenGlobalISel.inc13763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
13923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
13966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT,
13999 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15859 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
15927 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
16267 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
16335 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18551 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18755 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
18823 GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16691 { Mips::SLT, Mips::SLT, Mips::SLT_MM },
16691 { Mips::SLT, Mips::SLT, Mips::SLT_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 5025 case Mips::SLT:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 3996 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
4401 OpCode = Mips::SLT;
4436 OpRegCode = Mips::SLT;
4493 OpCode = Mips::SLT;
4569 FinalOpcode = Mips::SLT;
lib/Target/Mips/MipsFastISel.cpp 683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
lib/Target/Mips/MipsInstructionSelector.cpp 672 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
675 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
679 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
682 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);