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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7674 { 8379 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7681 { 8379 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7697 { 8441 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc16183 /* 29902*/ OPC_EmitNode1, TARGET_VAL(Mips::SLLV), 0,
19643 /* 36706*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLV), 0,
gen/lib/Target/Mips/MipsGenFastISel.inc 2024 return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenGlobalISel.inc12615 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV,
12956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16690 { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },
16690 { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 5233 case Mips::SLLV:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 4666 SecondShift = Mips::SLLV;
4669 FirstShift = Mips::SLLV;
lib/Target/Mips/MipsFastISel.cpp 2022 Opcode = Mips::SLLV;
lib/Target/Mips/MipsISelLowering.cpp 1686 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1689 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1867 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1872 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1876 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)