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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7299 { 7191 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
7676 { 8379 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7683 { 8379 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
gen/lib/Target/Mips/MipsGenAsmWriter.inc 9316 case Mips::SLL:
gen/lib/Target/Mips/MipsGenDAGISel.inc16170 /* 29870*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL), 0,
19577 /* 36582*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL), 0,
21456 /* 40034*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL), 0,
gen/lib/Target/Mips/MipsGenFastISel.inc 3639 return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/Mips/MipsGenGlobalISel.inc12288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12427 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL,
12881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16689 { Mips::SLL, Mips::SLL, Mips::SLL_MM },
16689 { Mips::SLL, Mips::SLL, Mips::SLL_MM },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 5301 case Mips::SLL:
gen/lib/Target/Mips/MipsGenMCPseudoLowering.inc 302 TmpInst.setOpcode(Mips::SLL);
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 3571 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3589 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
4271 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
4317 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
4729 FirstShift = Mips::SLL;
4734 SecondShift = Mips::SLL;
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 189 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 285 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
292 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
lib/Target/Mips/MipsAnalyzeImmediate.cpp 136 SLL = Mips::SLL;
lib/Target/Mips/MipsAsmPrinter.cpp 1215 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
lib/Target/Mips/MipsExpandPseudo.cpp 183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
463 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
lib/Target/Mips/MipsFastISel.cpp 1618 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1646 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1648 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1999 Opcode = Mips::SLL;
lib/Target/Mips/MipsISelLowering.cpp 1562 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1677 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1682 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1858 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1863 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
lib/Target/Mips/MipsInstructionSelector.cpp 318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
lib/Target/Mips/MipsSEISelLowering.cpp 3341 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;