reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc
 7612   { 8092 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc
24830 /* 46528*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
24852 /* 46582*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
24874 /* 46637*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
24896 /* 46691*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
24950 /* 46821*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25008 /* 46970*/        OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25067 /* 47121*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25125 /* 47269*/        OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25171 /* 47384*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25193 /* 47438*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25222 /* 47508*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25244 /* 47562*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25291 /* 47677*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25356 /* 47841*/        OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25408 /* 47977*/          OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
25473 /* 48140*/        OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
28937 /* 54738*/      OPC_MorphNodeTo1, TARGET_VAL(Mips::SHF_H), 0,
gen/lib/Target/Mips/MipsGenGlobalISel.inc
 3203       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3227       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3251       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3275       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3590       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3614       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3638       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3662       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3902       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3926       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3950       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3974       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 3998       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 4022       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 4046       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
 4070       GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc
 8220     case Mips::SHF_H: