reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenInstrInfo.inc
 5167   { 352,	1,	0,	4,	1004,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr },  // Inst #352 = JALR64Pseudo
 5168   { 353,	1,	0,	4,	1004,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr },  // Inst #353 = JALRHB64Pseudo
 5256   { 441,	1,	0,	4,	1012,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #441 = PseudoIndirectBranch64
 5257   { 442,	1,	0,	4,	1016,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #442 = PseudoIndirectBranch64R6
 5262   { 447,	1,	0,	4,	1012,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #447 = PseudoIndirectHazardBranch64
 5263   { 448,	1,	0,	4,	1016,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #448 = PseudoIndrectHazardBranch64R6
 5290   { 475,	1,	0,	4,	1008,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #475 = PseudoReturn64
 5374   { 559,	1,	0,	4,	1015,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr },  // Inst #559 = TAILCALL64R6REG
 5375   { 560,	1,	0,	4,	1015,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr },  // Inst #560 = TAILCALLHB64R6REG
 5379   { 564,	1,	0,	4,	1007,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr },  // Inst #564 = TAILCALLREG64
 5381   { 566,	1,	0,	4,	1007,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr },  // Inst #566 = TAILCALLREGHB64
 6484   { 1669,	1,	0,	4,	1003,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1669 = JR64
 6490   { 1675,	1,	0,	4,	1006,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1675 = JR_HB64
 6491   { 1676,	1,	0,	4,	1014,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1676 = JR_HB64_R6
 6709   { 1894,	1,	1,	4,	898,	0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1894 = MFHI64
 6715   { 1900,	1,	1,	4,	898,	0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1900 = MFLO64
 6852   { 2037,	1,	0,	4,	900,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo86, -1 ,nullptr },  // Inst #2037 = MTHI64
 6859   { 2044,	1,	0,	4,	900,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo86, -1 ,nullptr },  // Inst #2044 = MTLO64
 6863   { 2048,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo86, -1 ,nullptr },  // Inst #2048 = MTM0
 6864   { 2049,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo86, -1 ,nullptr },  // Inst #2049 = MTM1
 6865   { 2050,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo86, -1 ,nullptr },  // Inst #2050 = MTM2
 6866   { 2051,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo86, -1 ,nullptr },  // Inst #2051 = MTP0
 6867   { 2052,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo86, -1 ,nullptr },  // Inst #2052 = MTP1
 6868   { 2053,	1,	0,	4,	1197,	0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo86, -1 ,nullptr },  // Inst #2053 = MTP2