|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4994 { 179, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = AND_V_W_PSEUDO
5234 { 419, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #419 = NOR_V_W_PSEUDO
5237 { 422, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #422 = OR_V_W_PSEUDO
5400 { 585, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #585 = XOR_V_W_PSEUDO
5435 { 620, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #620 = ADDS_A_W
5439 { 624, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #624 = ADDS_S_W
5443 { 628, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #628 = ADDS_U_W
5466 { 651, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #651 = ADDV_W
5472 { 657, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #657 = ADD_A_W
5504 { 689, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #689 = ASUB_S_W
5508 { 693, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #693 = ASUB_U_W
5516 { 701, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #701 = AVER_S_W
5520 { 705, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #705 = AVER_U_W
5524 { 709, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #709 = AVE_S_W
5528 { 713, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #713 = AVE_U_W
5572 { 757, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #757 = BCLR_W
5681 { 866, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #866 = BNEG_W
5718 { 903, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #903 = BSET_W
5759 { 944, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #944 = CEQ_W
5783 { 968, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #968 = CLE_S_W
5787 { 972, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #972 = CLE_U_W
5803 { 988, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #988 = CLT_S_W
5807 { 992, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #992 = CLT_U_W
6086 { 1271, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1271 = DIV_S_W
6090 { 1275, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1275 = DIV_U_W
6248 { 1433, 3, 1, 4, 655, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1433 = FADD_W
6250 { 1435, 3, 1, 4, 572, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1435 = FCAF_W
6252 { 1437, 3, 1, 4, 573, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1437 = FCEQ_W
6256 { 1441, 3, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1441 = FCLE_W
6258 { 1443, 3, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1443 = FCLT_W
6265 { 1450, 3, 1, 4, 576, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1450 = FCNE_W
6267 { 1452, 3, 1, 4, 577, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1452 = FCOR_W
6269 { 1454, 3, 1, 4, 578, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1454 = FCUEQ_W
6271 { 1456, 3, 1, 4, 579, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1456 = FCULE_W
6273 { 1458, 3, 1, 4, 580, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1458 = FCULT_W
6275 { 1460, 3, 1, 4, 581, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1460 = FCUNE_W
6277 { 1462, 3, 1, 4, 582, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1462 = FCUN_W
6286 { 1471, 3, 1, 4, 650, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1471 = FDIV_W
6290 { 1475, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1475 = FEXP2_W
6323 { 1508, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1508 = FMAX_A_W
6325 { 1510, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1510 = FMAX_W
6327 { 1512, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1512 = FMIN_A_W
6329 { 1514, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1514 = FMIN_W
6348 { 1533, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1533 = FMUL_W
6364 { 1549, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1549 = FSAF_W
6366 { 1551, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1551 = FSEQ_W
6368 { 1553, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1553 = FSLE_W
6370 { 1555, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1555 = FSLT_W
6372 { 1557, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1557 = FSNE_W
6374 { 1559, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1559 = FSOR_W
6391 { 1576, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1576 = FSUB_W
6393 { 1578, 3, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1578 = FSUEQ_W
6395 { 1580, 3, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1580 = FSULE_W
6397 { 1582, 3, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1582 = FSULT_W
6399 { 1584, 3, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1584 = FSUNE_W
6401 { 1586, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1586 = FSUN_W
6433 { 1618, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1618 = ILVEV_W
6437 { 1622, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1622 = ILVL_W
6441 { 1626, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1626 = ILVOD_W
6445 { 1630, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1630 = ILVR_W
6676 { 1861, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1861 = MAX_A_W
6684 { 1869, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1869 = MAX_S_W
6688 { 1873, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1873 = MAX_U_W
6735 { 1920, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1920 = MIN_A_W
6743 { 1928, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1928 = MIN_S_W
6747 { 1932, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1932 = MIN_U_W
6757 { 1942, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1942 = MOD_S_W
6761 { 1946, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1946 = MOD_U_W
6892 { 2077, 3, 1, 4, 667, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2077 = MULR_Q_W
6910 { 2095, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2095 = MULV_W
6916 { 2101, 3, 1, 4, 668, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2101 = MUL_Q_W
6973 { 2158, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2158 = PCKEV_W
6977 { 2162, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2162 = PCKOD_W
7240 { 2425, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2425 = SLL_W
7275 { 2460, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2460 = SRAR_W
7282 { 2467, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2467 = SRA_W
7297 { 2482, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2482 = SRLR_W
7304 { 2489, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2489 = SRL_W
7330 { 2515, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2515 = SUBSUS_U_W
7334 { 2519, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2519 = SUBSUU_S_W
7338 { 2523, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2523 = SUBS_S_W
7342 { 2527, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2527 = SUBS_U_W
7365 { 2550, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2550 = SUBV_W