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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenInstrInfo.inc 5209 { 394, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #394 = MIPSeh_return64
6061 { 1246, 2, 1, 4, 842, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1246 = DBITSWAP
6062 { 1247, 2, 1, 4, 812, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1247 = DCLO
6063 { 1248, 2, 1, 4, 840, 0, 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1248 = DCLO_R6
6064 { 1249, 2, 1, 4, 813, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1249 = DCLZ
6065 { 1250, 2, 1, 4, 841, 0, 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1250 = DCLZ_R6
6111 { 1296, 2, 0, 4, 894, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo111, -1 ,nullptr }, // Inst #1296 = DMULT
6112 { 1297, 2, 0, 4, 895, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo111, -1 ,nullptr }, // Inst #1297 = DMULTu
6143 { 1328, 2, 1, 4, 1195, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1328 = DPOP
6169 { 1354, 2, 1, 4, 819, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1354 = DSBH
6170 { 1355, 2, 0, 4, 896, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo111, -1 ,nullptr }, // Inst #1355 = DSDIV
6171 { 1356, 2, 1, 4, 820, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1356 = DSHD
6184 { 1369, 2, 0, 4, 897, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo111, -1 ,nullptr }, // Inst #1369 = DUDIV
6463 { 1648, 2, 1, 4, 1004, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo111, -1 ,nullptr }, // Inst #1648 = JALR64
6470 { 1655, 2, 1, 4, 1005, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1655 = JALR_HB64
7130 { 2315, 2, 1, 4, 802, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2315 = SEB64
7133 { 2318, 2, 1, 4, 803, 0, 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2318 = SEH64
7228 { 2413, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2413 = SLL64_64