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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 7075 { 6467 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7323 { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7330 { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenAsmWriter.inc 9195 case Mips::OR:
gen/lib/Target/Mips/MipsGenDAGISel.inc 3634 /* 6612*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
3649 /* 6646*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
3711 /* 6790*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
3734 /* 6850*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
3762 /* 6918*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
3785 /* 6978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
5151 /* 9899*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
18407 /* 34476*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
gen/lib/Target/Mips/MipsGenFastISel.inc 1858 return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenGlobalISel.inc 2351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
17749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16663 { Mips::OR, Mips::OR, Mips::OR_MM },
16663 { Mips::OR, Mips::OR, Mips::OR_MM },
16800 { Mips::OR, Mips::OR, Mips::OR_MMR6 },
16800 { Mips::OR, Mips::OR, Mips::OR_MMR6 },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 5018 case Mips::OR:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 4082 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
4085 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4272 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4318 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4378 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4566 FinalOpcode = Mips::OR;
4681 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4744 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4806 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4901 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 114 return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp 261 case Mips::OR:
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 1297 Inst.setOpcode(Mips::OR);
lib/Target/Mips/MipsAsmPrinter.cpp 1092 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
lib/Target/Mips/MipsExpandPseudo.cpp 160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
233 MOVE = Mips::OR;
365 Opcode = Mips::OR;
440 BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
537 Opcode = Mips::OR;
548 OR = Mips::OR;
lib/Target/Mips/MipsFastISel.cpp 308 Opc = Mips::OR;
1620 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1643 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1649 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1650 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 140 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
lib/Target/Mips/MipsSEInstrInfo.cpp 95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
191 case Mips::OR: