reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc

 7141   { 6684 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },

gen/lib/Target/Mips/MipsGenDAGISel.inc

24745 /* 46345*/          OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1), 0,
27284 /* 51636*/          OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1), 0,
27317 /* 51699*/          OPC_EmitNode1, TARGET_VAL(Mips::MTC1), 0,

gen/lib/Target/Mips/MipsGenFastISel.inc

   65     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);

gen/lib/Target/Mips/MipsGenGlobalISel.inc

 2856       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,

gen/lib/Target/Mips/MipsGenInstrInfo.inc

16649   { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },
16649   { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },
16797   { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },
16797   { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 },

gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc

 7610     case Mips::MTC1:

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 3319     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
 3449       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
 3452       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
 3453       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);

lib/Target/Mips/MipsAsmPrinter.cpp

  877   if (Opcode == Mips::MTC1) {
  917   unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;

lib/Target/Mips/MipsCallLowering.cpp

  157     MIRBuilder.buildInstr(Mips::MTC1)

lib/Target/Mips/MipsFastISel.cpp

  397     emitInst(Mips::MTC1, DestReg).addReg(TempReg);

lib/Target/Mips/MipsInstructionSelector.cpp

  489           B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});

lib/Target/Mips/MipsRegisterBankInfo.cpp

  149   case Mips::MTC1:

lib/Target/Mips/MipsSEISelLowering.cpp

 3776                          : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);

lib/Target/Mips/MipsSEInstrInfo.cpp

  122       Opc = Mips::MTC1;
  453     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
  457     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
  464     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
  820   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);