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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 6871 { 5604 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 640 /* 1075*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
745 /* 1268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
1331 /* 2369*/ OPC_EmitNode1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
1342 /* 2396*/ OPC_EmitNode1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
6606 /* 12834*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16614 { Mips::LW, Mips::LW, Mips::LW_MM },
16614 { Mips::LW, Mips::LW, Mips::LW_MM },
16794 { Mips::LW, Mips::LW, Mips::LW_MMR6 },
16794 { Mips::LW, Mips::LW, Mips::LW_MMR6 },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 6566 case Mips::LW:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 2872 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg,
2877 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg,
2917 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg,
2984 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg,
3216 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),
3406 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3407 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
5054 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 224 case Mips::LW:
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 298 emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
lib/Target/Mips/MicroMipsSizeReduction.cpp 240 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
242 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
355 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM ||
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
lib/Target/Mips/MipsBranchExpansion.cpp 505 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
lib/Target/Mips/MipsFastISel.cpp 422 emitInst(Mips::LW, DestReg)
439 emitInst(Mips::LW, DestReg)
766 Opc = Mips::LW;
lib/Target/Mips/MipsInstructionSelector.cpp 189 return Mips::LW;
335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
lib/Target/Mips/MipsSEInstrInfo.cpp 49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
338 Opc = Mips::LW;
367 Opc = Mips::LW;
371 Opc = Mips::LW;