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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenInstrInfo.inc 5060 { 245, 1, 0, 4, 911, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #245 = BAL_BR
5061 { 246, 1, 0, 4, 938, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #246 = BAL_BR_MM
5167 { 352, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr }, // Inst #352 = JALR64Pseudo
5168 { 353, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr }, // Inst #353 = JALRHB64Pseudo
5169 { 354, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #354 = JALRHBPseudo
5170 { 355, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #355 = JALRPseudo
5171 { 356, 1, 0, 4, 982, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #356 = JAL_MMR6
5540 { 725, 1, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #725 = BAL
5541 { 726, 1, 0, 4, 918, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #726 = BALC
5542 { 727, 1, 0, 4, 991, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #727 = BALC_MMR6
5581 { 766, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #766 = BEQZALC
5582 { 767, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #767 = BEQZALC_MMR6
5597 { 782, 2, 0, 4, 917, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #782 = BGEZAL
5598 { 783, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #783 = BGEZALC
5599 { 784, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #784 = BGEZALC_MMR6
5600 { 785, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #785 = BGEZALL
5601 { 786, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #786 = BGEZALS_MM
5602 { 787, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #787 = BGEZAL_MM
5610 { 795, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #795 = BGTZALC
5611 { 796, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #796 = BGTZALC_MMR6
5639 { 824, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #824 = BLEZALC
5640 { 825, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #825 = BLEZALC_MMR6
5654 { 839, 2, 0, 4, 911, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #839 = BLTZAL
5655 { 840, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #840 = BLTZALC
5656 { 841, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #841 = BLTZALC_MMR6
5657 { 842, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #842 = BLTZALL
5658 { 843, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #843 = BLTZALS_MM
5659 { 844, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #844 = BLTZAL_MM
5684 { 869, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #869 = BNEZALC
5685 { 870, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo97, -1 ,nullptr }, // Inst #870 = BNEZALC_MMR6
6460 { 1645, 1, 0, 4, 401, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1645 = JAL
6461 { 1646, 2, 1, 4, 402, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #1646 = JALR
6462 { 1647, 1, 0, 2, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #1647 = JALR16_MM
6463 { 1648, 2, 1, 4, 1004, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo111, -1 ,nullptr }, // Inst #1648 = JALR64
6464 { 1649, 1, 0, 2, 993, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #1649 = JALRC16_MMR6
6466 { 1651, 2, 1, 4, 995, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #1651 = JALRC_MMR6
6467 { 1652, 1, 0, 2, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #1652 = JALRS16_MM
6468 { 1653, 2, 1, 4, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #1653 = JALRS_MM
6471 { 1656, 2, 1, 4, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #1656 = JALR_MM
6472 { 1657, 1, 0, 4, 953, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1657 = JALS_MM
6473 { 1658, 1, 0, 4, 404, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1658 = JALX
6474 { 1659, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1659 = JALX_MM
6475 { 1660, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1660 = JAL_MM
6476 { 1661, 2, 0, 4, 920, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1661 = JIALC
6477 { 1662, 2, 0, 4, 1013, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo101, -1 ,nullptr }, // Inst #1662 = JIALC64
6478 { 1663, 2, 0, 4, 996, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1663 = JIALC_MMR6
6495 { 1680, 1, 0, 6, 933, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1680 = Jal16
6496 { 1681, 1, 0, 6, 933, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1681 = JalB16
6500 { 1685, 1, 0, 2, 934, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo261, -1 ,nullptr }, // Inst #1685 = JumpLinkReg16