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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 6395 { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6396 { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6498 { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6500 { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
gen/lib/Target/Mips/MipsGenAsmWriter.inc 8877 case Mips::DSUBu:
gen/lib/Target/Mips/MipsGenDAGISel.inc18253 /* 34168*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSUBu), 0,
24654 /* 46167*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSUBu), 0|OPFL_GlueOutput,
gen/lib/Target/Mips/MipsGenFastISel.inc 2395 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2489 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenGlobalISel.inc 1307 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 4989 case Mips::DSUBu:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 4772 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4803 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 106 return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
lib/Target/Mips/MipsExpandPseudo.cpp 554 Opcode = Mips::DSUBu;