reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc

 6275   { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
 6277   { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
 7079   { 6467 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },

gen/lib/Target/Mips/MipsGenAsmWriter.inc

 8785   case Mips::DADDu:

gen/lib/Target/Mips/MipsGenDAGISel.inc

15946 /* 29421*/          OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDu), 0,
21418 /* 39955*/      OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDu), 0|OPFL_GlueOutput,

gen/lib/Target/Mips/MipsGenFastISel.inc

 1249     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 1340     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Mips/MipsGenGlobalISel.inc

  934         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,

gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc

 4976     case Mips::DADDu:

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 2638   unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
 2870         TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg,
 2915       TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg,
 2927         TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
 2992       TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
 3041       TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
 3066       TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
 3068         TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
 3091         TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
 3662       TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
 5177     TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

   98   return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

  265   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
 1285   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);

lib/Target/Mips/MipsBranchExpansion.cpp

  613       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)

lib/Target/Mips/MipsExpandPseudo.cpp

  551     Opcode = Mips::DADDu;

lib/Target/Mips/MipsMachineFunction.cpp

   90     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)