reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc

 5539   { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
 5546   { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },

gen/lib/Target/Mips/MipsGenDAGISel.inc

12439 /* 23192*/            OPC_MorphNodeTo1, TARGET_VAL(Mips::AND), 0,

gen/lib/Target/Mips/MipsGenFastISel.inc

 1386     return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Mips/MipsGenGlobalISel.inc

 2181         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,

gen/lib/Target/Mips/MipsGenInstrInfo.inc

16481   { Mips::AND, Mips::AND, Mips::AND_MM },
16481   { Mips::AND, Mips::AND, Mips::AND_MM },
16774   { Mips::AND, Mips::AND, Mips::AND_MMR6 },
16774   { Mips::AND, Mips::AND, Mips::AND_MMR6 },

gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc

 4972     case Mips::AND:

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 4560       FinalOpcode = Mips::AND;

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

  110   return ArePtrs64bit() ? Mips::AND64 : Mips::AND;

lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp

  104     MaskInst.setOpcode(Mips::AND);

lib/Target/Mips/MipsExpandPseudo.cpp

  146   BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
  157   BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
  359     Opcode = Mips::AND;
  409     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  415     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  424     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  429     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  438   BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
  454   BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest)
  534     Opcode = Mips::AND;
  544     AND = Mips::AND;

lib/Target/Mips/MipsFastISel.cpp

  305     Opc = Mips::AND;

lib/Target/Mips/MipsISelLowering.cpp

 1853   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)

lib/Target/Mips/MipsSEFrameLowering.cpp

  419   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;