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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5500 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5506 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7076 { 6467 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
gen/lib/Target/Mips/MipsGenAsmWriter.inc 7501 case Mips::ADDu:
gen/lib/Target/Mips/MipsGenDAGISel.inc15919 /* 29373*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDu), 0,
16148 /* 29822*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDu), 0,
21404 /* 39930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDu), 0|OPFL_GlueOutput,
gen/lib/Target/Mips/MipsGenFastISel.inc 1240 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1331 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenGlobalISel.inc 831 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
12458 GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16480 { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },
16480 { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },
16773 { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },
16773 { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 4971 case Mips::ADDu:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 2638 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
2870 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg,
2915 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg,
2927 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
2992 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
3130 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3662 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
3705 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
4557 FinalOpcode = Mips::ADDu;
4917 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
5177 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp 98 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 265 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
330 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
359 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
396 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
1194 TmpInst.setOpcode(Mips::ADDu);
lib/Target/Mips/MicroMipsSizeReduction.cpp 222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
lib/Target/Mips/MipsBranchExpansion.cpp 502 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
lib/Target/Mips/MipsExpandPseudo.cpp 347 Opcode = Mips::ADDu;
528 Opcode = Mips::ADDu;
lib/Target/Mips/MipsFastISel.cpp 2119 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
lib/Target/Mips/MipsInstructionSelector.cpp 286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
lib/Target/Mips/MipsMachineFunction.cpp 119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
146 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)