reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
3561 if (VT == MVT::i32 && Predicate_immZExt5(imm1)) 3562 if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3565 if (VT == MVT::i32 && Predicate_immZExt6(imm1)) 3566 if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3569 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1)) 3570 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3573 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1)) 3574 if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3577 if (VT == MVT::i32 && Predicate_immZExt4(imm1)) 3578 if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3581 if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1)) 3582 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3585 if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1)) 3586 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3589 if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1)) 3590 if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3593 if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1)) 3594 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3598 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3599 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3600 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3601 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);