reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc
 2529     case MCK_SImm32: return true;
 2570     case MCK_SImm32: return true;
 2610     case MCK_SImm32: return true;
 2650     case MCK_SImm32: return true;
 2689     case MCK_SImm32: return true;
 2727     case MCK_SImm32: return true;
 2764     case MCK_SImm32: return true;
 2800     case MCK_SImm32: return true;
 2835     case MCK_SImm32: return true;
 2869     case MCK_SImm32: return true;
 2902     case MCK_SImm32: return true;
 2934     case MCK_SImm32: return true;
 2965     case MCK_SImm32: return true;
 2995     case MCK_SImm32: return true;
 3024     case MCK_SImm32: return true;
 3052     case MCK_SImm32: return true;
 3079     case MCK_SImm32: return true;
 3105     case MCK_SImm32: return true;
 3130     case MCK_SImm32: return true;
 3154     case MCK_SImm32: return true;
 3177     case MCK_SImm32: return true;
 3199     case MCK_SImm32: return true;
 3220     case MCK_SImm32: return true;
 3240     case MCK_SImm32: return true;
 3259     case MCK_SImm32: return true;
 3277     case MCK_SImm32: return true;
 3294     case MCK_SImm32: return true;
 3310     case MCK_SImm32: return true;
 3325     case MCK_SImm32: return true;
 3339     case MCK_SImm32: return true;
 3352     case MCK_SImm32: return true;
 3364     case MCK_SImm32: return true;
 3375     case MCK_SImm32: return true;
 3386     case MCK_SImm32: return true;
 3397     case MCK_SImm32: return true;
 3407     case MCK_SImm32: return true;
 3417     case MCK_SImm32: return true;
 3426     case MCK_SImm32: return true;
 3434     case MCK_SImm32: return true;
 3439   case MCK_SImm32:
 4157   case MCK_SImm32: {
 4761   case MCK_SImm32: return "MCK_SImm32";
 6320   { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
 6328   { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
 6346   { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
 6355   { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
 7568   { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
 7576   { 8056 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
 7579   { 8056 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
 7589   { 8065 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
 7593   { 8065 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },